firmware/lm32: now all warnings should be fixed

enjoy-digital · enjoy-digital · commit fa4a7562cc9e · 2016-01-23T11:07:43.000+01:00
diff --git a/firmware/lm32/ci.c b/firmware/lm32/ci.c
@@ -310,14 +310,11 @@ static void video_mode_set(int mode)
 
 static void hdp_toggle(int source)
 {
-#if defined(CSR_HDMI_IN0_BASE) || defined(CSR_HDMI_IN1_BASE)
-	int i;
-#endif
 	printf("Toggling HDP on output%d\n", source);
 #ifdef CSR_HDMI_IN0_BASE
 	if(source ==  VIDEO_IN_HDMI_IN0) {
 		hdmi_in0_edid_hpd_en_write(0);
-		for(i=0; i<65536; i++);
+		for(int i=0; i<65536; i++);
 		hdmi_in0_edid_hpd_en_write(1);
 	}
 #else
@@ -326,7 +323,7 @@ static void hdp_toggle(int source)
 #ifdef CSR_HDMI_IN1_BASE
 	if(source == VIDEO_IN_HDMI_IN1) {
 		hdmi_in1_edid_hpd_en_write(0);
-		for(i=0; i<65536; i++);
+		for(int i=0; i<65536; i++);
 		hdmi_in1_edid_hpd_en_write(1);
 	}
 #else
diff --git a/firmware/lm32/pll.c b/firmware/lm32/pll.c
@@ -27,31 +27,29 @@ static const unsigned short int pll_config_10x[32] = {
 
 static void program_data(const unsigned short *data)
 {
-	int i;
-
 	/*
 	 * Some bits of words 4 and 5 appear to depend on PLL location,
 	 * so we start at word 6.
 	 * PLLs also seem to dislike any write to the last words.
 	 */
 #ifdef CSR_HDMI_OUT0_BASE
-	for(i=6;i<32-5;i++) {
+	for(int i=6;i<32-5;i++) {
 		hdmi_out0_driver_clocking_pll_adr_write(i);
 		hdmi_out0_driver_clocking_pll_dat_w_write(data[i]);
 		hdmi_out0_driver_clocking_pll_write_write(1);
 		while(!hdmi_out0_driver_clocking_pll_drdy_read());
 	}
 #endif
 #ifdef CSR_HDMI_IN0_BASE
-	for(i=6;i<32-5;i++) {
+	for(int i=6;i<32-5;i++) {
 		hdmi_in0_clocking_pll_adr_write(i);
 		hdmi_in0_clocking_pll_dat_w_write(data[i]);
 		hdmi_in0_clocking_pll_write_write(1);
 		while(!hdmi_in0_clocking_pll_drdy_read());
 	}
 #endif
 #ifdef CSR_HDMI_IN1_BASE
-	for(i=6;i<32-5;i++) {
+	for(int i=6;i<32-5;i++) {
 		hdmi_in1_clocking_pll_adr_write(i);
 		hdmi_in1_clocking_pll_dat_w_write(data[i]);
 		hdmi_in1_clocking_pll_write_write(1);
@@ -84,11 +82,9 @@ void pll_config_for_clock(int freq)
 
 void pll_dump(void)
 {
-	int i;
-
 #ifdef CSR_HDMI_OUT0_BASE
 	printf("framebuffer PLL:\n");
-	for(i=0;i<32;i++) {
+	for(int i=0;i<32;i++) {
 		hdmi_out0_driver_clocking_pll_adr_write(i);
 		hdmi_out0_driver_clocking_pll_read_write(1);
 		while(!hdmi_out0_driver_clocking_pll_drdy_read());
@@ -98,7 +94,7 @@ void pll_dump(void)
 #endif
 #ifdef CSR_HDMI_IN0_BASE
 	printf("dvisampler0 PLL:\n");
-	for(i=0;i<32;i++) {
+	for(int i=0;i<32;i++) {
 		hdmi_in0_clocking_pll_adr_write(i);
 		hdmi_in0_clocking_pll_read_write(1);
 		while(!hdmi_in0_clocking_pll_drdy_read());
@@ -108,7 +104,7 @@ void pll_dump(void)
 #endif
 #ifdef CSR_HDMI_IN1_BASE
 	printf("dvisampler1 PLL:\n");
-	for(i=0;i<32;i++) {
+	for(int i=0;i<32;i++) {
 		hdmi_in1_clocking_pll_adr_write(i);
 		hdmi_in1_clocking_pll_read_write(1);
 		while(!hdmi_in1_clocking_pll_drdy_read());
diff --git a/firmware/lm32/processor.c b/firmware/lm32/processor.c
@@ -266,10 +266,9 @@ void processor_list_modes(char *mode_descriptors)
 
 static void fb_clkgen_write(int cmd, int data)
 {
+#ifdef CSR_HDMI_OUT0_BASE
 	int word;
-
 	word = (data << 2) | cmd;
-#ifdef CSR_HDMI_OUT0_BASE
 	hdmi_out0_driver_clocking_cmd_data_write(word);
 	hdmi_out0_driver_clocking_send_cmd_data_write(1);
 	while(hdmi_out0_driver_clocking_status_read() & CLKGEN_STATUS_BUSY);
@@ -349,16 +348,15 @@ static void edid_set_mode(const struct video_timing *mode)
 {
 #if defined(CSR_HDMI_IN0_BASE) || defined(CSR_HDMI_IN1_BASE)
 	unsigned char edid[128];
-	int i;
 #endif
 #ifdef CSR_HDMI_IN0_BASE
 	generate_edid(&edid, "OHW", "TV", 2015, "HDMI2USB 1", mode);
-	for(i=0;i<sizeof(edid);i++)
+	for(int i=0;i<sizeof(edid);i++)
 		MMPTR(CSR_HDMI_IN0_EDID_MEM_BASE+4*i) = edid[i];
 #endif
 #ifdef CSR_HDMI_IN1_BASE
 	generate_edid(&edid, "OHW", "TV", 2015, "HDMI2USB 2", mode);
-	for(i=0;i<sizeof(edid);i++)
+	for(int i=0;i<sizeof(edid);i++)
 		MMPTR(CSR_HDMI_IN1_EDID_MEM_BASE+4*i) = edid[i];
 #endif
 }
