targets: reduce encoder fifo_depth to 16

timvideos · Jan 25, 2016 · 5e11b6b · 5e11b6b
1 parent 8ffd745
commit 5e11b6b
Show file tree

Hide file tree

Showing 3 changed files with 3 additions and 3 deletions.
diff --git a/targets/atlys_hdmi2eth.py b/targets/atlys_hdmi2eth.py
@@ -125,7 +125,7 @@ def __init__(self, platform, **kwargs):
         self.submodules.encoder_cdc = RenameClockDomains(AsyncFIFO([("data", 128)], 4),
                                           {"write": "sys", "read": "encoder"})
         self.submodules.encoder_buffer = RenameClockDomains(EncoderBuffer(), "encoder")
-        self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 128), "encoder")
+        self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 16), "encoder")
         self.submodules.encoder = Encoder(platform)
         encoder_port = self.ethcore.udp.crossbar.get_port(8000, 8)
         self.submodules.encoder_streamer = UDPStreamer(convert_ip("192.168.1.15"), 8000)

diff --git a/targets/atlys_hdmi2usb.py b/targets/atlys_hdmi2usb.py
@@ -78,7 +78,7 @@ def __init__(self, platform, **kwargs):
         self.submodules.encoder_cdc = RenameClockDomains(AsyncFIFO([("data", 128)], 4),
                                           {"write": "sys", "read": "encoder"})
         self.submodules.encoder_buffer = RenameClockDomains(EncoderBuffer(), "encoder")
-        self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 128), "encoder")
+        self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 16), "encoder")
         self.submodules.encoder = Encoder(platform)
         self.submodules.encoder_streamer = USBStreamer(platform, platform.request("fx2"))
 

diff --git a/targets/opsis_hdmi2usb.py b/targets/opsis_hdmi2usb.py
@@ -78,7 +78,7 @@ def __init__(self, platform, **kwargs):
         self.submodules.encoder_cdc = RenameClockDomains(AsyncFIFO([("data", 128)], 4),
                                           {"write": "sys", "read": "encoder"})
         self.submodules.encoder_buffer = RenameClockDomains(EncoderBuffer(), "encoder")
-        self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 128), "encoder")
+        self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 16), "encoder")
         self.submodules.encoder = Encoder(platform)
         self.submodules.usb_streamer = USBStreamer(platform, platform.request("fx2"))