timvideos · Jan 25, 2016 · Jan 25, 2016
Showing with 18 additions and 4 deletions.

+1 −1 firmware/lm32/hdmi_in0.c

+1 −1 firmware/lm32/hdmi_in1.c

+14 −0 firmware/lm32/processor.c

+1 −1 firmware/lm32/processor.h

+1 −1 gateware/streamer/__init__.py
diff --git a/firmware/lm32/hdmi_in0.c b/firmware/lm32/hdmi_in0.c
@@ -21,7 +21,7 @@ int hdmi_in0_fb_index;
 #define FRAMEBUFFER_MASK (FRAMEBUFFER_COUNT - 1)
 
 #define HDMI_IN0_FRAMEBUFFERS_BASE 0x00000000
-#define HDMI_IN0_FRAMEBUFFERS_SIZE 1280*720*2
+#define HDMI_IN0_FRAMEBUFFERS_SIZE 1920*1080*2
 
 unsigned int hdmi_in0_framebuffer_base(char n) {
 	return HDMI_IN0_FRAMEBUFFERS_BASE + n*HDMI_IN0_FRAMEBUFFERS_SIZE;

diff --git a/firmware/lm32/hdmi_in1.c b/firmware/lm32/hdmi_in1.c
@@ -21,7 +21,7 @@ int hdmi_in1_fb_index;
 #define FRAMEBUFFER_MASK (FRAMEBUFFER_COUNT - 1)
 
 #define HDMI_IN1_FRAMEBUFFERS_BASE 0x01000000
-#define HDMI_IN1_FRAMEBUFFERS_SIZE 1280*720*2
+#define HDMI_IN1_FRAMEBUFFERS_SIZE 1920*1080*2
 
 unsigned int hdmi_in1_framebuffer_base(char n) {
 	return HDMI_IN1_FRAMEBUFFERS_BASE + n*HDMI_IN1_FRAMEBUFFERS_SIZE;

diff --git a/firmware/lm32/processor.c b/firmware/lm32/processor.c
@@ -252,6 +252,20 @@ static const struct video_timing video_modes[PROCESSOR_MODE_COUNT] = {
 		.v_blanking = 30,
 		.v_sync_offset = 5,
 		.v_sync_width = 5
+	},
+	// 1920x1080 @ 30.00 Hz    ModeLine "1920x1080" 89.01 1920 2448 2492 2640 1080 1084 1089 1125 +HSync +VSync
+	{
+		.pixel_clock = 8901,
+
+		.h_active = 1920,
+		.h_blanking = 720,
+		.h_sync_offset = 528,
+		.h_sync_width = 44,
+
+		.v_active = 1080,
+		.v_blanking = 45,
+		.v_sync_offset = 4,
+		.v_sync_width = 5
 	}
 };
 

diff --git a/firmware/lm32/processor.h b/firmware/lm32/processor.h
@@ -1,7 +1,7 @@
 #ifndef __PROCESSOR_H
 #define __PROCESSOR_H
 
-#define PROCESSOR_MODE_COUNT 11
+#define PROCESSOR_MODE_COUNT 12
 #define PROCESSOR_MODE_DESCLEN 32
 
 enum {

diff --git a/gateware/streamer/__init__.py b/gateware/streamer/__init__.py
@@ -92,7 +92,7 @@ def __init__(self, platform, pads):
         ]
 
         self.submodules.fifo = fifo = RenameClockDomains(AsyncFIFO([("data", 8)], 4),
-                                          {"write": "sys", "read": "usb"})
+                                          {"write": "encoder", "read": "usb"})
         self.comb += Record.connect(sink, fifo.sink)