opsis: share uart pads between FX2 and SD card pins

timvideos · Jan 27, 2016 · 9ac8965 · 9ac8965
1 parent ec9f88e
commit 9ac8965
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Showing 2 changed files with 30 additions and 8 deletions.
diff --git a/platforms/opsis.py b/platforms/opsis.py
@@ -241,11 +241,11 @@
     # Current use FX2 firmware from https://github.com/mithro/fx2lib/tree/cdc-usb-serialno-from-eeprom/examples/cdc/to-uart
     # FIXME: Will be supported by opsis-mode-switch --mode=serial soon.
     # FIXME: Will be supported by opsis-mode-siwtch --mode=jtag longer term.
-    ("serial", 0,
+    ("serial_fx2", 0,
         # CY_RXD1 - P18 - Cypress RXD0
         Subsignal("tx", Pins("P18"), IOStandard("LVCMOS33")),
         # CY_TXD1 - T17 - Cypress TXD0
-        Subsignal("rx", Pins("T17"), IOStandard("LVCMOS33")),
+        Subsignal("rx", Pins("T17"), IOStandard("LVCMOS33"), Misc("PULLUP")),
     ),
     # To Cypress FX2 UART1
     #("serial", 1,
@@ -254,12 +254,12 @@
     #),
     #
     # Florent's UART (requires desoldering 2 resistors on the SD card connector)
-    #("serial", 0,
-    #    # SD_CMD
-    #    Subsignal("tx", Pins("U6"), IOStandard("LVCMOS33")),
-    #    # SD_DAT0
-    #    Subsignal("rx", Pins("AA4"), IOStandard("LVCMOS33")),
-    #),
+    ("serial_sd_card", 0,
+        # SD_CMD
+        Subsignal("tx", Pins("U6"), IOStandard("LVCMOS33")),
+        # SD_DAT0
+        Subsignal("rx", Pins("AA4"), IOStandard("LVCMOS33"), Misc("PULLUP")),
+    ),
 
     ## onboard HDMI OUT1
     ## HDMI - connector J3 - Direction TX

diff --git a/targets/opsis_base.py b/targets/opsis_base.py
@@ -14,6 +14,8 @@
 from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
 from misoclib.soc import mem_decoder
 from misoclib.soc.sdram import SDRAMSoC
+from misoclib.com.uart.phy import UARTPHY
+from misoclib.com import uart
 
 from liteeth.phy.s6rgmii import LiteEthPHYRGMII
 from liteeth.core.mac import LiteEthMAC
@@ -124,6 +126,11 @@ def __init__(self, platform, clk_freq):
         self.specials += AsyncResetSynchronizer(self.cd_encoder, self.cd_sys.rst)
 
 
+class UARTSharedPads:
+    def __init__(self):
+        self.tx = Signal()
+        self.rx = Signal()
+
 class BaseSoC(SDRAMSoC):
     default_platform = "opsis"
 
@@ -152,13 +159,28 @@ def __init__(self, platform,
         SDRAMSoC.__init__(self, platform, clk_freq,
                           integrated_rom_size=0x8000,
                           sdram_controller_settings=LASMIconSettings(l2_size=32, with_bandwidth=True),
+                          with_uart=False,
                           **kwargs)
 
         self.submodules.crg = _CRG(platform, clk_freq)
         self.submodules.dna = dna.DNA()
         self.submodules.git_info = git_info.GitInfo()
         self.submodules.platform_info = platform_info.PlatformInfo("opsis", self.__class__.__name__[:8])
 
+
+        fx2_uart_pads = platform.request("serial_fx2")
+        sd_card_uart_pads = platform.request("serial_sd_card")
+        uart_pads = UARTSharedPads()
+        self.comb += [
+          # TX
+          fx2_uart_pads.tx.eq(uart_pads.tx),
+          sd_card_uart_pads.tx.eq(uart_pads.tx),
+          # RX
+          uart_pads.rx.eq(fx2_uart_pads.rx & sd_card_uart_pads.rx)
+        ]
+        self.submodules.uart_phy = UARTPHY(uart_pads, self.clk_freq, 115200)
+        self.submodules.uart = uart.UART(self.uart_phy)
+
 #        self.submodules.opsis_eeprom_i2c = i2c.I2C(platform.request("opsis_eeprom"))
         self.submodules.fx2_reset = gpio.GPIOOut(platform.request("fx2_reset"))
         self.submodules.fx2_hack = i2c_hack.I2CShiftReg(platform.request("opsis_eeprom"))