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base repository: timvideos/HDMI2USB-litex-firmware
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head repository: timvideos/HDMI2USB-litex-firmware
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compare: 4621a6e4caa8
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  • 3 commits
  • 4 files changed
  • 1 contributor

Commits on Jan 25, 2016

  1. atlys: adapt hdmi2usb to new encoder buffer

    @enjoy-digital
    enjoy-digital committed Jan 25, 2016
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    b1421a9 View commit details

  2. atlys: adapt hdmi2eth to new encoder buffer

    @enjoy-digital
    enjoy-digital committed Jan 25, 2016
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    cf5e1c8 View commit details

  3. gateware/streamer: add asyncfifo on UDPStreamer

    @enjoy-digital
    enjoy-digital committed Jan 25, 2016
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    4621a6e View commit details
Showing with 43 additions and 13 deletions.
  1. +3 −2 gateware/streamer/__init__.py
  2. +3 −0 targets/atlys_base.py
  3. +17 −4 targets/atlys_hdmi2eth.py
  4. +20 −7 targets/atlys_hdmi2usb.py
5 changes: 3 additions & 2 deletions gateware/streamer/__init__.py
View file
Original file line number Diff line number Diff line change
@@ -3,7 +3,7 @@
from migen.fhdl.std import *
from migen.genlib.record import *
from migen.flow.actor import *
from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
from migen.actorlib.fifo import AsyncFIFO
from migen.genlib.misc import WaitTimer

from liteeth.common import *
@@ -15,7 +15,8 @@ def __init__(self, ip_address, udp_port, fifo_depth=1024):

# # #

self.submodules.fifo = fifo = SyncFIFO([("data", 8)], fifo_depth)
self.submodules.fifo = fifo = RenameClockDomains(AsyncFIFO([("data", 8)], fifo_depth),
{"write": "encoder", "read": "sys"})
self.comb += Record.connect(sink, fifo.sink)

level = Signal(max=fifo_depth + 1)
3 changes: 3 additions & 0 deletions targets/atlys_base.py
View file
Original file line number Diff line number Diff line change
@@ -28,6 +28,7 @@ def __init__(self, platform, clk_freq):
self.clock_domains.cd_sdram_full_wr = ClockDomain()
self.clock_domains.cd_sdram_full_rd = ClockDomain()
self.clock_domains.cd_base50 = ClockDomain()
self.clock_domains.cd_encoder = ClockDomain()

self.clk4x_wr_strb = Signal()
self.clk4x_rd_strb = Signal()
@@ -109,6 +110,8 @@ def __init__(self, platform, clk_freq):
self.specials += AsyncResetSynchronizer(self.cd_base50, self.cd_sys.rst | ~dcm_base50_locked)
platform.add_period_constraint(self.cd_base50.clk, 20)

self.comb += self.cd_encoder.clk.eq(self.cd_sys.clk)
self.specials += AsyncResetSynchronizer(self.cd_encoder, self.cd_sys.rst)

class BaseSoC(SDRAMSoC):
default_platform = "atlys"
21 changes: 17 additions & 4 deletions targets/atlys_hdmi2eth.py
View file
Original file line number Diff line number Diff line change
@@ -9,8 +9,13 @@

from gateware.hdmi_in import HDMIIn
from gateware.hdmi_out import HDMIOut
from gateware.encoder import EncoderReader, Encoder
from gateware.encoder import Encoder
from gateware.encoder.dma import EncoderDMAReader
from gateware.encoder.buffer import EncoderBuffer
from gateware.streamer import UDPStreamer
from migen.actorlib.fifo import AsyncFIFO, SyncFIFO
from migen.flow.actor import *


class EtherboneSoC(BaseSoC):
csr_peripherals = (
@@ -115,17 +120,25 @@ class HDMI2ETHSoC(VideomixerSoC):
def __init__(self, platform, **kwargs):
VideomixerSoC.__init__(self, platform, **kwargs)

self.submodules.encoder_reader = EncoderReader(self.sdram.crossbar.get_master())
lasmim = self.sdram.crossbar.get_master()
self.submodules.encoder_reader = EncoderDMAReader(lasmim)
self.submodules.encoder_cdc = RenameClockDomains(AsyncFIFO([("data", 128)], 4),
{"write": "sys", "read": "encoder"})
self.submodules.encoder_buffer = RenameClockDomains(EncoderBuffer(), "encoder")
self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 128), "encoder")
self.submodules.encoder = Encoder(platform)
encoder_port = self.ethcore.udp.crossbar.get_port(8000, 8)
self.submodules.encoder_streamer = UDPStreamer(convert_ip("192.168.1.15"), 8000)

self.comb += [
platform.request("user_led", 0).eq(self.encoder_reader.source.stb),
platform.request("user_led", 1).eq(self.encoder_reader.source.ack),
Record.connect(self.encoder_reader.source, self.encoder.sink),
Record.connect(self.encoder_reader.source, self.encoder_cdc.sink),
Record.connect(self.encoder_cdc.source, self.encoder_buffer.sink),
Record.connect(self.encoder_buffer.source, self.encoder_fifo.sink),
Record.connect(self.encoder_fifo.source, self.encoder.sink),
Record.connect(self.encoder.source, self.encoder_streamer.sink),
Record.connect(self.encoder_streamer.source, encoder_port.sink)
Record.connect(self.encoder_streamer.source, self.encoder.port.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), self.encoder.bus)
self.add_memory_region("encoder", self.mem_map["encoder"]+self.shadow_base, 0x2000)
27 changes: 20 additions & 7 deletions targets/atlys_hdmi2usb.py
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,15 @@
from targets.atlys_base import *
from targets.atlys_base import default_subtarget as BaseSoC
from targets.common import *
from targets.opsis_base import *
from targets.opsis_base import default_subtarget as BaseSoC

from gateware.hdmi_in import HDMIIn
from gateware.hdmi_out import HDMIOut
from gateware.encoder import EncoderReader, Encoder
from gateware.encoder import Encoder
from gateware.encoder.dma import EncoderDMAReader
from gateware.encoder.buffer import EncoderBuffer
from gateware.streamer import USBStreamer
from migen.actorlib.fifo import AsyncFIFO, SyncFIFO
from migen.flow.actor import *

class VideomixerSoC(BaseSoC):
csr_peripherals = (
@@ -68,15 +73,23 @@ class HDMI2USBSoC(VideomixerSoC):
def __init__(self, platform, **kwargs):
VideomixerSoC.__init__(self, platform, **kwargs)

self.submodules.encoder_reader = EncoderReader(self.sdram.crossbar.get_master())
lasmim = self.sdram.crossbar.get_master()
self.submodules.encoder_reader = EncoderDMAReader(lasmim)
self.submodules.encoder_cdc = RenameClockDomains(AsyncFIFO([("data", 128)], 4),
{"write": "sys", "read": "encoder"})
self.submodules.encoder_buffer = RenameClockDomains(EncoderBuffer(), "encoder")
self.submodules.encoder_fifo = RenameClockDomains(SyncFIFO(EndpointDescription([("data", 16)], packetized=True), 128), "encoder")
self.submodules.encoder = Encoder(platform)
self.submodules.usb_streamer = USBStreamer(platform, platform.request("fx2"))
self.submodules.encoder_streamer = USBStreamer(platform, platform.request("fx2"))

self.comb += [
platform.request("user_led", 0).eq(self.encoder_reader.source.stb),
platform.request("user_led", 1).eq(self.encoder_reader.source.ack),
Record.connect(self.encoder_reader.source, self.encoder.sink),
Record.connect(self.encoder.source, self.usb_streamer.sink)
Record.connect(self.encoder_reader.source, self.encoder_cdc.sink),
Record.connect(self.encoder_cdc.source, self.encoder_buffer.sink),
Record.connect(self.encoder_buffer.source, self.encoder_fifo.sink),
Record.connect(self.encoder_fifo.source, self.encoder.sink),
Record.connect(self.encoder.source, self.encoder_streamer.sink)
]
self.add_wb_slave(mem_decoder(self.mem_map["encoder"]), self.encoder.bus)
self.add_memory_region("encoder", self.mem_map["encoder"]+self.shadow_base, 0x2000)