atlys: fix hdmi2eth and hdmi2usb

timvideos · Jan 25, 2016 · ec78175 · ec78175
1 parent 55569bf
commit ec78175
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Showing 2 changed files with 9 additions and 5 deletions.
diff --git a/gateware/streamer/__init__.py b/gateware/streamer/__init__.py
@@ -3,7 +3,7 @@
 from migen.fhdl.std import *
 from migen.genlib.record import *
 from migen.flow.actor import *
-from migen.actorlib.fifo import AsyncFIFO
+from migen.actorlib.fifo import SyncFIFO, AsyncFIFO
 from migen.genlib.misc import WaitTimer
 
 from liteeth.common import *
@@ -15,9 +15,13 @@ def __init__(self, ip_address, udp_port, fifo_depth=1024):
 
         # # #
 
-        self.submodules.fifo = fifo = RenameClockDomains(AsyncFIFO([("data", 8)], fifo_depth),
+        self.submodules.async_fifo = async_fifo = RenameClockDomains(AsyncFIFO([("data", 8)], 4),
                                           {"write": "encoder", "read": "sys"})
-        self.comb += Record.connect(sink, fifo.sink)
+        self.submodules.fifo = fifo = SyncFIFO([("data", 8)], fifo_depth)
+        self.comb += [
+            Record.connect(sink, async_fifo.sink),
+            Record.connect(async_fifo.source, fifo.sink)
+        ]
 
         level = Signal(max=fifo_depth + 1)
         level_update = Signal()

diff --git a/targets/atlys_hdmi2usb.py b/targets/atlys_hdmi2usb.py
@@ -1,6 +1,6 @@
 from targets.common import *
-from targets.opsis_base import *
-from targets.opsis_base import default_subtarget as BaseSoC
+from targets.atlys_base import *
+from targets.atlys_base import default_subtarget as BaseSoC
 
 from gateware.hdmi_in import HDMIIn
 from gateware.hdmi_out import HDMIOut