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opsis: use 66MHz clock for encoder
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enjoy-digital committed Jan 25, 2016
1 parent 4621a6e commit 55569bf
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions targets/opsis_base.py
Expand Up @@ -67,7 +67,7 @@ def __init__(self, platform, clk_freq):
o_CLKOUT4=pll[4], p_CLKOUT4_DUTY_CYCLE=.5,
o_CLKOUT5=pll[5], p_CLKOUT5_DUTY_CYCLE=.5,
p_CLKOUT0_PHASE=0., p_CLKOUT0_DIVIDE=p//8, # sdram wr rd
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=p//8,
p_CLKOUT1_PHASE=0., p_CLKOUT1_DIVIDE=6,
p_CLKOUT2_PHASE=230., p_CLKOUT2_DIVIDE=p//4, # sdram dqs adr ctrl
p_CLKOUT3_PHASE=210., p_CLKOUT3_DIVIDE=p//4, # off-chip ddr
p_CLKOUT4_PHASE=0., p_CLKOUT4_DIVIDE=p//2,
Expand Down Expand Up @@ -116,7 +116,7 @@ def __init__(self, platform, clk_freq):
self.specials += AsyncResetSynchronizer(self.cd_base50, self.cd_sys.rst | ~dcm_base50_locked)
platform.add_period_constraint(self.cd_base50.clk, 20)

self.comb += self.cd_encoder.clk.eq(self.cd_sys.clk)
self.specials += Instance("BUFG", i_I=pll[1], o_O=self.cd_encoder.clk) # 66 MHz
self.specials += AsyncResetSynchronizer(self.cd_encoder, self.cd_sys.rst)


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