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  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Jan 21, 2016

  1. add information about CLOCK hardware

    @sbourdeauducq
    sbourdeauducq committed Jan 21, 2016
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    fa1afb7 View commit details

  2. gateware: clean up and integrate QC2 modifications from Daniel

    @sbourdeauducq
    sbourdeauducq committed Jan 21, 2016
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    b3ba97e View commit details
Showing with 129 additions and 43 deletions.
  1. +76 −0 artiq/gateware/nist_clock.py
  2. +15 −27 artiq/gateware/nist_qc2.py
  3. +18 −15 artiq/gateware/targets/kc705.py
  4. +20 −1 doc/manual/core_device.rst
76 changes: 76 additions & 0 deletions artiq/gateware/nist_clock.py
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,76 @@
from migen.build.generic_platform import *


fmc_adapter_io = [
("ttl", 0, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
("ttl", 1, Pins("LPC:LA02_P"), IOStandard("LVTTL")),
("ttl", 2, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
("ttl", 3, Pins("LPC:LA02_N"), IOStandard("LVTTL")),
("ttl", 4, Pins("LPC:LA01_CC_N"), IOStandard("LVTTL")),
("ttl", 5, Pins("LPC:LA06_P"), IOStandard("LVTTL")),
("ttl", 6, Pins("LPC:LA06_N"), IOStandard("LVTTL")),
("ttl", 7, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
("ttl", 8, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
("ttl", 9, Pins("LPC:LA05_N"), IOStandard("LVTTL")),
("ttl", 10, Pins("LPC:LA05_P"), IOStandard("LVTTL")),
("ttl", 11, Pins("LPC:LA09_P"), IOStandard("LVTTL")),
("ttl", 12, Pins("LPC:LA09_N"), IOStandard("LVTTL")),
("ttl", 13, Pins("LPC:LA13_P"), IOStandard("LVTTL")),
("ttl", 14, Pins("LPC:LA14_P"), IOStandard("LVTTL")),
("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),

("pmt", 0, Pins("LPC:CLK0_M2C_P"), IOStandard("LVTTL")),
("pmt", 1, Pins("LPC:CLK0_M2C_N"), IOStandard("LVTTL")),

("dds", 0,
Subsignal("a", Pins("LPC:LA22_N LPC:LA21_P LPC:LA22_P LPC:LA19_N "
"LPC:LA20_N LPC:LA19_P LPC:LA20_P")),
Subsignal("d", Pins("LPC:LA15_N LPC:LA16_N LPC:LA15_P LPC:LA16_P "
"LPC:LA11_N LPC:LA12_N LPC:LA11_P LPC:LA12_P "
"LPC:LA07_N LPC:LA08_N LPC:LA07_P LPC:LA08_P "
"LPC:LA04_N LPC:LA03_N LPC:LA04_P LPC:LA03_P")),
Subsignal("sel_n", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
"LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N "
"LPC:LA30_N LPC:LA33_P LPC:LA33_N")),
Subsignal("fud", Pins("LPC:LA21_N")),
Subsignal("wr_n", Pins("LPC:LA24_P")),
Subsignal("rd_n", Pins("LPC:LA25_N")),
Subsignal("rst", Pins("LPC:LA25_P")),
IOStandard("LVTTL")),

("i2c", 0,
Subsignal("scl", Pins("LPC:IIC_SLC")),
Subsignal("sda", Pins("LPC:IIC_SDA")),
IOStandard("LVCMOS25")),

("clk_m2c", 1,
Subsignal("p", Pins("LPC:CLK1_M2C_P")),
Subsignal("n", Pins("LPC:CLK1_M2C_N")),
IOStandard("LVDS")),

("la32", 0,
Subsignal("p", Pins("LPC:LA32_P")),
Subsignal("n", Pins("LPC:LA32_N")),
IOStandard("LVDS")),

("spi", 0,
Subsignal("clk", Pins("LPC:LA13_N")),
Subsignal("ce", Pins("LPC:LA14_N")),
Subsignal("mosi", Pins("LPC:LA17_CC_P")),
Subsignal("miso", Pins("LPC:LA17_CC_N")),
IOStandard("LVTTL")),

("spi", 1,
Subsignal("clk", Pins("LPC:LA23_N")),
Subsignal("ce", Pins("LPC:LA23_P")),
Subsignal("mosi", Pins("LPC:LA18_CC_N")),
Subsignal("miso", Pins("LPC:LA18_CC_P")),
IOStandard("LVTTL")),

("spi", 2,
Subsignal("clk", Pins("LPC:LA27_P")),
Subsignal("ce", Pins("LPC:LA26_P")),
Subsignal("mosi", Pins("LPC:LA27_N")),
Subsignal("miso", Pins("LPC:LA26_N")),
IOStandard("LVTTL")),
]
42 changes: 15 additions & 27 deletions artiq/gateware/nist_qc2.py
View file
Original file line number Diff line number Diff line change
@@ -18,6 +18,19 @@
("ttl", 13, Pins("LPC:LA09_N"), IOStandard("LVTTL")),
("ttl", 14, Pins("LPC:LA13_P"), IOStandard("LVTTL")),
("ttl", 15, Pins("LPC:LA14_P"), IOStandard("LVTTL")),
("ttl", 16, Pins("LPC:LA13_N"), IOStandard("LVTTL")),
("ttl", 17, Pins("LPC:LA14_N"), IOStandard("LVTTL")),
("ttl", 18, Pins("LPC:LA17_CC_P"), IOStandard("LVTTL")),
("ttl", 19, Pins("LPC:LA17_CC_N"), IOStandard("LVTTL")),
("ttl", 20, Pins("LPC:LA18_CC_P"), IOStandard("LVTTL")),
("ttl", 21, Pins("LPC:LA18_CC_N"), IOStandard("LVTTL")),
("ttl", 22, Pins("LPC:LA23_P"), IOStandard("LVTTL")),
("ttl", 23, Pins("LPC:LA23_N"), IOStandard("LVTTL")),
("ttl", 24, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
("ttl", 25, Pins("LPC:LA26_P"), IOStandard("LVTTL")),
("ttl", 26, Pins("LPC:LA27_N"), IOStandard("LVTTL")),
("ttl", 27, Pins("LPC:LA26_N"), IOStandard("LVTTL")),


("dds", 0,
Subsignal("a", Pins("LPC:LA22_N LPC:LA21_P LPC:LA22_P LPC:LA19_N "
@@ -28,15 +41,15 @@
"LPC:LA04_N LPC:LA03_N LPC:LA04_P LPC:LA03_P")),
Subsignal("sel_n", Pins("LPC:LA24_N LPC:LA29_P LPC:LA28_P LPC:LA29_N "
"LPC:LA28_N LPC:LA31_P LPC:LA30_P LPC:LA31_N "
"LPC:LA30_N LPC:LA33_P LPC:LA33_N")),
"LPC:LA30_N LPC:LA33_P LPC:LA33_N LPC:LA32_P")),
Subsignal("fud", Pins("LPC:LA21_N")),
Subsignal("wr_n", Pins("LPC:LA24_P")),
Subsignal("rd_n", Pins("LPC:LA25_N")),
Subsignal("rst", Pins("LPC:LA25_P")),
IOStandard("LVTTL")),

("i2c", 0,
Subsignal("scl", Pins("LPC:IIC_SLC")),
Subsignal("scl", Pins("LPC:IIC_SCL")),
Subsignal("sda", Pins("LPC:IIC_SDA")),
IOStandard("LVCMOS25")),

@@ -50,29 +63,4 @@
Subsignal("n", Pins("LPC:CLK1_M2C_N")),
IOStandard("LVDS")),

("la32", 0,
Subsignal("p", Pins("LPC:LA32_P")),
Subsignal("n", Pins("LPC:LA32_N")),
IOStandard("LVDS")),

("spi", 0,
Subsignal("clk", Pins("LPC:LA13_N")),
Subsignal("ce", Pins("LPC:LA14_N")),
Subsignal("mosi", Pins("LPC:LA17_CC_P")),
Subsignal("miso", Pins("LPC:LA17_CC_N")),
IOStandard("LVTTL")),

("spi", 1,
Subsignal("clk", Pins("LPC:LA18_CC_P")),
Subsignal("ce", Pins("LPC:LA18_CC_N")),
Subsignal("mosi", Pins("LPC:LA23_P")),
Subsignal("miso", Pins("LPC:LA23_N")),
IOStandard("LVTTL")),

("spi", 2,
Subsignal("clk", Pins("LPC:LA27_P")),
Subsignal("ce", Pins("LPC:LA26_P")),
Subsignal("mosi", Pins("LPC:LA27_N")),
Subsignal("miso", Pins("LPC:LA26_N")),
IOStandard("LVTTL")),
]
33 changes: 18 additions & 15 deletions artiq/gateware/targets/kc705.py
View file
Original file line number Diff line number Diff line change
@@ -213,25 +213,27 @@ def __init__(self, cpu_type="or1k", **kwargs):


class NIST_QC2(_NIST_QCx):
"""
NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
and 12 DDS channels. Current implementation for single backplane.
"""
def __init__(self, cpu_type="or1k", **kwargs):
_NIST_QCx.__init__(self, cpu_type, **kwargs)

platform = self.platform
platform.add_extension(nist_qc2.fmc_adapter_io)

rtio_channels = []
for i in range(16):
if i == 14:
# TTL14 is for the clock generator
continue
if i % 4 == 3:
phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
else:
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
# TTL0-23 are In+Out capable
for i in range(24):
phy = ttl_serdes_7series.Inout_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=512))
# TTL24-26 are output only
for i in range(24, 27):
phy = ttl_serdes_7series.Output_8X(platform.request("ttl", i))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))

phy = ttl_simple.Inout(platform.request("user_sma_gpio_n"))
self.submodules += phy
@@ -241,15 +243,16 @@ def __init__(self, cpu_type="or1k", **kwargs):
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)

phy = ttl_simple.ClockGen(platform.request("ttl", 14))
# TTL27 is for the clock generator
phy = ttl_simple.ClockGen(platform.request("ttl", 27))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))

self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
self.config["DDS_CHANNEL_COUNT"] = 11
self.config["DDS_CHANNEL_COUNT"] = 12
self.config["DDS_AD9914"] = True
self.config["DDS_ONEHOT_SEL"] = True
phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
phy = dds.AD9914(platform.request("dds"), 12, onehot=True)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=512,
21 changes: 20 additions & 1 deletion doc/manual/core_device.rst
View file
Original file line number Diff line number Diff line change
@@ -27,7 +27,7 @@ FPGA board ports
KC705
-----

The main target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST QC1 hardware via an adapter, and the NIST QC2 hardware (FMC).
The main target board for the ARTIQ core device is the KC705 development board from Xilinx. It supports the NIST QC1 hardware via an adapter, and the NIST CLOCK and QC2 hardware (FMC).

With the QC1 hardware, the TTL lines are mapped as follows:

@@ -47,6 +47,25 @@ With the QC1 hardware, the TTL lines are mapped as follows:
| 19 | TTL15 | Clock |
+--------------+------------+--------------+

With the CLOCK hardware, the TTL lines are mapped as follows:

+--------------------+-----------------------+--------------+
| RTIO channel | TTL line | Capability |
+====================+=======================+==============+
| 3,7,11,15 | TTL3,7,11,15 | Input+Output |
+--------------------+-----------------------+--------------+
| 0-2,4-6,8-10,12-14 | TTL0-2,4-6,8-10,12-14 | Output |
+--------------------+-----------------------+--------------+
| 16 | PMT0 | Input |
+--------------------+-----------------------+--------------+
| 17 | PMT1 | Input |
+--------------------+-----------------------+--------------+
| 18 | SMA_GPIO_N | Input+Output |
+--------------------+-----------------------+--------------+
| 19 | LED | Output |
+--------------------+-----------------------+--------------+


Pipistrello
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