sinara: fix fpga id string

m-labs · Mar 11, 2017 · 42e73fd · 42e73fd
1 parent 953e3f0
commit 42e73fd
Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/migen/build/platforms/sinara/metlino.py b/migen/build/platforms/sinara/metlino.py
@@ -42,4 +42,4 @@ class Platform(XilinxPlatform):
     default_clk_period = 20.0
 
     def __init__(self):
-        XilinxPlatform.__init__(self, "xcku040-ffva1156-1", _io, toolchain="vivado")
+        XilinxPlatform.__init__(self, "xcku040-ffva1156-1-c", _io, toolchain="vivado")
diff --git a/migen/build/platforms/sinara/sayma_amc.py b/migen/build/platforms/sinara/sayma_amc.py
@@ -65,4 +65,4 @@ class Platform(XilinxPlatform):
     default_clk_period = 20.0
 
     def __init__(self):
-        XilinxPlatform.__init__(self, "xcku040-ffva1156-1", _io, toolchain="vivado")
+        XilinxPlatform.__init__(self, "xcku040-ffva1156-1-c", _io, toolchain="vivado")