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sinara: fix fpga id string
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sbourdeauducq committed Mar 11, 2017
1 parent 953e3f0 commit 42e73fd
Showing 2 changed files with 2 additions and 2 deletions.
2 changes: 1 addition & 1 deletion migen/build/platforms/sinara/metlino.py
Original file line number Diff line number Diff line change
@@ -42,4 +42,4 @@ class Platform(XilinxPlatform):
default_clk_period = 20.0

def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-1", _io, toolchain="vivado")
XilinxPlatform.__init__(self, "xcku040-ffva1156-1-c", _io, toolchain="vivado")
2 changes: 1 addition & 1 deletion migen/build/platforms/sinara/sayma_amc.py
Original file line number Diff line number Diff line change
@@ -65,4 +65,4 @@ class Platform(XilinxPlatform):
default_clk_period = 20.0

def __init__(self):
XilinxPlatform.__init__(self, "xcku040-ffva1156-1", _io, toolchain="vivado")
XilinxPlatform.__init__(self, "xcku040-ffva1156-1-c", _io, toolchain="vivado")

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