It will be put in misoc during integration

…I flash and SDRAM in targets (until validated)

…rty as a logic analyzer over ethernet)

as of SVN revision 778 of XC3Sprog, the ARTY XC7A35T is not yet
supported by XC3Sprog.

You need to add this line in devlist.txt and recompile:
0362D093      6    0x09 XC7A35T

You can then use cable nexys4 to load the FPGA bitstream.

…x constraints, add IDelayCtrl

We will have to see how write leveling can be done or decrease frequency and avoid write leveling.

… from PLL and use MiniSoC as default target

The qemu-build script pulls the spiflash model from the
platforms/arty.py file.  If it is not available qemu will crash as the
argument will have 'serial='.

This will fix that issue.

platforms/arty: Add spiflash model for qemu-build