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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Apr 13, 2016

  1. typo

    @sbourdeauducq
    sbourdeauducq committed Apr 13, 2016
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    582efe5 View commit details

  2. manual/installing: --toolchain vivado

    @sbourdeauducq
    sbourdeauducq committed Apr 13, 2016
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Showing with 3 additions and 1 deletion.
  1. +1 −1 doc/manual/faq.rst
  2. +2 −0 doc/manual/installing.rst
2 changes: 1 addition & 1 deletion doc/manual/faq.rst
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@@ -99,7 +99,7 @@ The core device tests require the following TTL devices and connections:

* ``ttl_out``: any output-only TTL.
* ``ttl_out_serdes``: any output-only TTL that uses a SERDES (i.e. has a fine timestamp). Can be aliased to ``ttl_out``.
* ``loop_out``: : any output-only TTL. Must be physically connected to ``loop_in``. Can be aliased to ``ttl_out``.
* ``loop_out``: any output-only TTL. Must be physically connected to ``loop_in``. Can be aliased to ``ttl_out``.
* ``loop_in``: any input-capable TTL. Must be physically connected to ``loop_out``.
* ``loop_clock_out``: a clock generator TTL. Must be physically connected to ``loop_clock_in``.
* ``loop_clock_in``: any input-capable TTL. Must be physically connected to ``loop_clock_out``.
2 changes: 2 additions & 0 deletions doc/manual/installing.rst
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@@ -265,6 +265,8 @@ These steps are required to generate gateware bitstream (``.bit``) files, build

$ python3.5 -m artiq.gateware.targets.kc705 -H qc1 # or qc2

.. note:: Add ``--toolchain vivado`` if you wish to use Vivado instead of ISE.

* Then, gather the binaries and flash them: ::

$ mkdir binaries