cores/liteeth_mini/mac/sram: fix reception of frames larger than MTU

-use 32bits length CSR (allow software to detect frames larger than MTU) -drop remaining bytes
m-labs · May 1, 2016 · e136030 · sbourdeauducq · May 3, 2016 · enjoy-digital
1 parent 6e86189
commit e136030
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/misoc/cores/liteeth_mini/mac/sram.py b/misoc/cores/liteeth_mini/mac/sram.py
@@ -3,7 +3,7 @@
 from misoc.interconnect.csr import *
 from misoc.interconnect.csr_eventmanager import *
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.common import eth_phy_layout
+from misoc.cores.liteeth_mini.common import eth_phy_layout, eth_mtu
 
 
 class LiteEthMACSRAMWriter(Module, AutoCSR):
@@ -12,7 +12,7 @@ def __init__(self, dw, depth, nslots=2):
         self.crc_error = Signal()
 
         slotbits = max(log2_int(nslots), 1)
-        lengthbits = log2_int(depth*4)  # length in bytes
+        lengthbits = 32
 
         self._slot = CSRStatus(slotbits)
         self._length = CSRStatus(lengthbits)
@@ -74,7 +74,7 @@ def __init__(self, dw, depth, nslots=2):
         )
         fsm.act("WRITE",
             counter_ce.eq(sink.stb),
-            ongoing.eq(1),
+            ongoing.eq(counter < eth_mtu),
             If(sink.stb & sink.eop,
                 If((sink.error & sink.last_be) != 0,
                     NextState("DISCARD")