Revert "liteeth: use non power-of-two RAM depth"

This reverts commit a512d82.
m-labs · Apr 30, 2016 · 6e86189 · 6e86189
1 parent fe550f3
commit 6e86189
Showing 3 changed files with 6 additions and 5 deletions.
diff --git a/misoc/cores/liteeth_mini/common.py b/misoc/cores/liteeth_mini/common.py
@@ -4,6 +4,7 @@
 eth_min_len = 46
 eth_interpacket_gap = 12
 eth_preamble = 0xD555555555555555
+buffer_depth = 2**log2_int(eth_mtu, need_pow2=False)
 
 
 def eth_phy_layout(dw):

diff --git a/misoc/cores/liteeth_mini/mac/sram.py b/misoc/cores/liteeth_mini/mac/sram.py
@@ -12,7 +12,7 @@ def __init__(self, dw, depth, nslots=2):
         self.crc_error = Signal()
 
         slotbits = max(log2_int(nslots), 1)
-        lengthbits = bits_for(depth*4)  # length in bytes
+        lengthbits = log2_int(depth*4)  # length in bytes
 
         self._slot = CSRStatus(slotbits)
         self._length = CSRStatus(lengthbits)
@@ -130,7 +130,7 @@ def __init__(self, dw, depth, nslots=2):
         self.source = source = stream.Endpoint(eth_phy_layout(dw))
 
         slotbits = max(log2_int(nslots), 1)
-        lengthbits = bits_for(depth*4)  # length in bytes
+        lengthbits = log2_int(depth*4)  # length in bytes
         self.lengthbits = lengthbits
 
         self._start = CSR()

diff --git a/misoc/cores/liteeth_mini/mac/wishbone.py b/misoc/cores/liteeth_mini/mac/wishbone.py
@@ -4,7 +4,7 @@
 from misoc.interconnect import wishbone
 from misoc.interconnect.csr import *
 from misoc.interconnect import stream
-from misoc.cores.liteeth_mini.common import eth_phy_layout, eth_mtu
+from misoc.cores.liteeth_mini.common import eth_phy_layout, buffer_depth
 from misoc.cores.liteeth_mini.mac import sram
 
 
@@ -17,7 +17,7 @@ def __init__(self, dw, nrxslots=2, ntxslots=2):
         # # #
 
         # storage in SRAM
-        sram_depth = eth_mtu//(dw//8)
+        sram_depth = buffer_depth//(dw//8)
         self.submodules.sram = sram.LiteEthMACSRAM(dw, sram_depth, nrxslots, ntxslots)
         self.comb += [
             self.sink.connect(self.sram.sink),
@@ -33,7 +33,7 @@ def __init__(self, dw, nrxslots=2, ntxslots=2):
         wb_sram_ifs = wb_rx_sram_ifs + wb_tx_sram_ifs
 
         wb_slaves = []
-        decoderoffset = log2_int(sram_depth, need_pow2=False)
+        decoderoffset = log2_int(sram_depth)
         decoderbits = log2_int(len(wb_sram_ifs))
         for n, wb_sram_if in enumerate(wb_sram_ifs):
             def slave_filter(a, v=n):