opsis: add I2C to gateware

timvideos · Aug 21, 2015 · 7ee9cda · 7ee9cda
1 parent 54a6203
commit 7ee9cda
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Showing 6 changed files with 58 additions and 26 deletions.
diff --git a/hdl/i2c.py b/hdl/i2c.py
@@ -0,0 +1,22 @@
+from migen.fhdl.std import *
+from migen.fhdl.specials import Tristate
+from migen.bank.description import *
+
+
+class I2C(Module, AutoCSR):
+    def __init__(self, pads):
+        self._w = CSRStorage(8, name="w")
+        self._r = CSRStatus(1, name="r")
+
+    # # #
+
+        _sda_w = Signal()
+        _sda_oe = Signal()
+        _sda_r = Signal()
+        self.comb +=[
+            pads.scl.eq(self._w.storage[0]),
+            _sda_oe.eq(self._w.storage[1]),
+            _sda_w.eq(self._w.storage[2]),
+            self._r.status[0].eq(_sda_r)
+        ]
+        self.specials +=Tristate(pads.sda, _sda_w, _sda_oe, _sda_r)
diff --git a/platforms/opsis.py b/platforms/opsis.py
@@ -112,6 +112,11 @@
         #Subsignal("sda", Pins("C1"), IOStandard("I2C")),
     ),
 
+    ("i2c", 0,
+        Subsignal("scl", Pins("G6")),
+        Subsignal("sda", Pins("C1")),
+    ),
+
     ## onBoard Quad-SPI Flash
     ## W25Q128FVEIG - component U3
     ## 128M (16M x 8) - 104MHz

diff --git a/targets/atlys_hdmi2ethernet.py b/targets/atlys_hdmi2ethernet.py
@@ -14,8 +14,8 @@
 
 class EtherboneSoC(BaseSoC):
     csr_map = {
-        "ethphy": 17,
-        "ethcore": 18,
+        "ethphy":  18,
+        "ethcore": 19,
     }
     csr_map.update(BaseSoC.csr_map)
 
@@ -55,9 +55,9 @@ def __init__(self, platform,
 
 class VideomixerSoC(EtherboneSoC):
     csr_map = {
-        "fb":                  19,
-        "dvisampler":          20,
-        "dvisampler_edid_mem": 21
+        "fb":                  20,
+        "dvisampler":          21,
+        "dvisampler_edid_mem": 22
     }
     csr_map.update(EtherboneSoC.csr_map)
 
@@ -83,8 +83,8 @@ def __init__(self, platform, **kwargs):
 
 class HDMI2EthernetSoC(VideomixerSoC):
     csr_map = {
-        "encoder_reader": 22
-        "encoder"       : 23
+        "encoder_reader": 23
+        "encoder"       : 24
     }
     csr_map.update(VideomixerSoC.csr_map)
     mem_map = {

diff --git a/targets/atlys_hdmi2usb.py b/targets/atlys_hdmi2usb.py
@@ -9,12 +9,12 @@
 
 class VideomixerSoC(opsis_base_soc):
     csr_map = {
-        "fb0":                  19,
-        "fb1":                  20,
-        "dvisampler0":          21,
-        "dvisampler0_edid_mem": 22,
-        "dvisampler1":          23,
-        "dvisampler1_edid_mem": 24,
+        "fb0":                  20,
+        "fb1":                  21,
+        "dvisampler0":          22,
+        "dvisampler0_edid_mem": 23,
+        "dvisampler1":          24,
+        "dvisampler1_edid_mem": 25,
     }
     csr_map.update(opsis_base_soc.csr_map)
 
@@ -56,8 +56,8 @@ def __init__(self, platform, **kwargs):
 
 class HDMI2USBSoC(VideomixerSoC):
     csr_map = {
-        "encoder_reader": 25,
-        "encoder":        26
+        "encoder_reader": 26,
+        "encoder":        27
     }
     csr_map.update(VideomixerSoC.csr_map)
     mem_map = {

diff --git a/targets/opsis_base.py b/targets/opsis_base.py
@@ -17,6 +17,7 @@
 from misoclib.com.liteeth.core.mac import LiteEthMAC
 
 from hdl import s6ddrphy
+from hdl import i2c
 
 # DDR3
 class MT41J128M16(SDRAMModule):
@@ -149,7 +150,8 @@ class BaseSoC(SDRAMSoC):
     default_platform = "opsis"
 
     csr_map = {
-        "ddrphy":   16,
+        "ddrphy": 16,
+        "i2c":    17
     }
     csr_map.update(SDRAMSoC.csr_map)
 
@@ -170,9 +172,12 @@ def __init__(self, platform,
 
         self.submodules.crg = _CRG(platform, clk_freq)
 
+        self.submodules.i2c = i2c.I2C(platform.request("i2c"))
+
         self.submodules.firmware_ram = wishbone.SRAM(firmware_ram_size, init=_get_firmware_data(firmware_filename))
         self.register_mem("firmware_ram", self.mem_map["firmware_ram"], self.firmware_ram.bus, firmware_ram_size)
         self.add_constant("ROM_BOOT_ADDRESS", self.mem_map["firmware_ram"])
+
         if not self.integrated_main_ram_size:
             self.submodules.ddrphy = s6ddrphy.S6QuarterRateDDRPHY(platform.request("ddram"),
                                                                   MT41J128M16(self.clk_freq),
@@ -193,8 +198,8 @@ def __init__(self, platform,
 
 class MiniSoC(BaseSoC):
     csr_map = {
-        "ethphy": 17,
-        "ethmac": 18,
+        "ethphy": 18,
+        "ethmac": 19,
     }
     csr_map.update(BaseSoC.csr_map)
 

diff --git a/targets/opsis_hdmi2usb.py b/targets/opsis_hdmi2usb.py
@@ -9,12 +9,12 @@
 
 class VideomixerSoC(opsis_base_soc):
     csr_map = {
-        "fb0":                  19,
-        "fb1":                  20,
-        "dvisampler0":          21,
-        "dvisampler0_edid_mem": 22,
-        "dvisampler1":          23,
-        "dvisampler1_edid_mem": 24,
+        "fb0":                  20,
+        "fb1":                  21,
+        "dvisampler0":          22,
+        "dvisampler0_edid_mem": 23,
+        "dvisampler1":          24,
+        "dvisampler1_edid_mem": 25,
     }
     csr_map.update(opsis_base_soc.csr_map)
 
@@ -56,8 +56,8 @@ def __init__(self, platform, **kwargs):
 
 class HDMI2USBSoC(VideomixerSoC):
     csr_map = {
-        "encoder_reader": 25,
-        "encoder":        26
+        "encoder_reader": 26,
+        "encoder":        27
     }
     csr_map.update(VideomixerSoC.csr_map)
     mem_map = {