Adding UrJTAG support.

timvideos · Jul 5, 2015 · b144f0d · b144f0d
1 parent a0951b7
commit b144f0d
Showing 1 changed file with 3 additions and 1 deletion.
diff --git a/platforms/atlys.py b/platforms/atlys.py
@@ -1,6 +1,6 @@
 from mibuild.generic_platform import *
 from mibuild.xilinx import XilinxPlatform
-from mibuild.xilinx import XC3SProg, iMPACT, Adept
+from mibuild.xilinx import XC3SProg, iMPACT, Adept, UrJTAG
 
 # There appear to be 4 x LTC2481C on the U1-SCL / U1-SDA lines connected to the Cypress
 
@@ -569,6 +569,8 @@ def create_programmer(self):
         elif self.programmer == "fpgalink":
             from mibuild.fpgalink_programmer import FPGALink
             return FPGALink("1443:0007")
+        elif self.programmer == "urjtag":
+            return UrJTAG(cable="USBBlaster", pld="spartan-6")
         else:
             raise ValueError("{} programmer is not supported".format(programmer))