platforms/kc705: use correct IO voltage for user_sma_gpio_{p,n}.

Its bank is FPGA_VADJ, which is 2.5V by default.
m-labs · Jun 11, 2016 · 5630b7c · 5630b7c
1 parent 73f9b87
commit 5630b7c
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/migen/build/platforms/kc705.py b/migen/build/platforms/kc705.py
@@ -35,8 +35,8 @@
     ("user_sma_clock_p", 0, Pins("L25"), IOStandard("LVCMOS25")),
     ("user_sma_clock_n", 0, Pins("K25"), IOStandard("LVCMOS25")),
 
-    ("user_sma_gpio_p", 0, Pins("Y23"), IOStandard("LVCMOS33")),
-    ("user_sma_gpio_n", 0, Pins("Y24"), IOStandard("LVCMOS33")),
+    ("user_sma_gpio_p", 0, Pins("Y23"), IOStandard("LVCMOS25")),
+    ("user_sma_gpio_n", 0, Pins("Y24"), IOStandard("LVCMOS25")),
 
     ("clk200", 0,
         Subsignal("p", Pins("AD12"), IOStandard("LVDS")),