spi: cross-reference bit ordering and alignment, closes #482

m-labs · Jun 15, 2016 · a8b211f · a8b211f
1 parent 033aa33
commit a8b211f
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/artiq/coredevice/spi.py b/artiq/coredevice/spi.py
@@ -196,6 +196,7 @@ def write(self, data=0):
           deasserting ``cs`` in between. Once a transfer completes,
           the previous transfer's read data is available in the
           ``data`` register.
+        * For bit alignment and bit ordering see :meth:`set_config`.
 
         This method advances the timeline by the duration of the SPI transfer.
         If a transfer is to be chained, the timeline needs to be rewound.
@@ -207,6 +208,8 @@ def write(self, data=0):
     def read_async(self):
         """Trigger an asynchronous read from the ``data`` register.
 
+        For bit alignment and bit ordering see :meth:`set_config`.
+
         Reads always finish in two cycles.
 
         Every data register read triggered by a :meth:`read_async`