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  • 3 commits
  • 7 files changed
  • 1 contributor

Commits on Sep 2, 2016

  1. 3
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    72dda5e View commit details
  2. sawg: coredevice api fixes

    jordens committed Sep 2, 2016
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    55e61f6 View commit details
  3. sawg: example ddb/experiment

    jordens committed Sep 2, 2016
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72 changes: 72 additions & 0 deletions artiq/coredevice/sawg.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,72 @@
from artiq.language.core import kernel, now_mu
from artiq.coredevice.rtio import rtio_output


class SAWG:
"""Smart arbitrary waveform generator channel.
:param channel_base: RTIO channel number of the first channel (amplitude).
Frequency and Phase are then assumed to be successive channels.
"""
kernel_invariants = {"amplitude_scale", "frequency_scale", "phase_scale",
"channel_base"}

def __init__(self, dmgr, channel_base, parallelism=4, core_device="core"):
self.core = dmgr.get(core_device)
self.channel_base = channel_base
cordic_gain = 1.646760258057163 # Cordic(width=16, guard=None).gain
a_width = 16
f_width = 48
p_width = 16
self.amplitude_scale = (1 << a_width) / 2 / cordic_gain
self.phase_scale = 1 << p_width
self.frequency_scale = ((1 << f_width) / self.core.coarse_ref_period /
parallelism)

@kernel
def set_amplitude_mu(self, amplitude=0):
"""Set DDS amplitude (machine units).
:param amplitude: DDS amplitude in machine units.
"""
rtio_output(now_mu(), self.channel_base, 0, amplitude)

@kernel
def set_amplitude(self, amplitude=0):
"""Set DDS amplitude.
:param amplitude: DDS amplitude relative to full-scale.
"""
self.set_amplitude_mu(amplitude*self.amplitude_scale)

@kernel
def set_frequency_mu(self, frequency=0):
"""Set DDS frequency (machine units).
:param frequency: DDS frequency in machine units.
"""
rtio_output(now_mu(), self.channel_base + 1, 0, frequency)

@kernel
def set_frequency(self, frequency=0):
"""Set DDS frequency.
:param frequency: DDS frequency in Hz.
"""
self.set_frequency_mu(frequency*self.frequency_scale)

@kernel
def set_phase_mu(self, phase=0):
"""Set DDS phase (machine units).
:param phase: DDS phase in machine units.
"""
rtio_output(now_mu(), self.channel_base + 2, 0, phase)

@kernel
def set_phase(self, phase=0):
"""Set DDS phase.
:param phase: DDS phase relative in turns.
"""
self.set_phase_mu(phase*self.phase_scale)
63 changes: 63 additions & 0 deletions artiq/examples/phaser/device_db.pyon
Original file line number Diff line number Diff line change
@@ -0,0 +1,63 @@
# The RTIO channel numbers here are for Phaser on KC705.

{
"comm": {
"type": "local",
"module": "artiq.coredevice.comm_tcp",
"class": "Comm",
"arguments": {"host": "kc705-phaser.lab.m-labs.hk"}
},
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"ref_period": 1e-9}
},
"core_cache": {
"type": "local",
"module": "artiq.coredevice.cache",
"class": "CoreCache"
},
"ttl_sma": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLInOut",
"arguments": {"channel": 0}
},
"led": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 1}
},
"dac0_spi": {
"type": "local",
"module": "artiq.coredevice.spi",
"class": "SPIMaster",
"arguments": {"channel": 2}
},
"sawg0": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 3, "parallelism": 4}
},
"sawg1": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 6, "parallelism": 4}
},
"sawg2": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 9, "parallelism": 4}
},
"sawg3": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 12, "parallelism": 4}
}
}
21 changes: 21 additions & 0 deletions artiq/examples/phaser/idle_kernel.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,21 @@
from artiq.experiment import *


class IdleKernel(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("led")

@kernel
def run(self):
start_time = now_mu() + seconds_to_mu(500*ms)
while self.core.get_rtio_counter_mu() < start_time:
pass
self.core.reset()
while True:
self.led.pulse(250*ms)
delay(125*ms)
self.led.pulse(125*ms)
delay(125*ms)
self.led.pulse(125*ms)
delay(250*ms)
35 changes: 35 additions & 0 deletions artiq/examples/phaser/repository/sawg.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
from artiq.experiment import *


class SAWGTest(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("led")

self.setattr_device("dac0_spi")
self.setattr_device("sawg0")
self.setattr_device("sawg1")
self.setattr_device("sawg2")
self.setattr_device("sawg3")

@kernel
def run(self):
self.core.reset()

delay(100*us)
self.sawg0.set_amplitude(.1)
self.sawg1.set_amplitude(-1)
self.sawg2.set_amplitude(.5)
self.sawg3.set_amplitude(.5)
self.sawg0.set_frequency(1*Mhz)
self.sawg1.set_frequency(100*Mhz)
self.sawg2.set_frequency(200*Mhz)
self.sawg3.set_frequency(200*Mhz)
self.sawg0.set_phase(0)
self.sawg1.set_phase(0)
self.sawg2.set_phase(0)
self.sawg3.set_phase(.5)

while True:
self.led.pulse(100*ms)
delay(100*ms)
2 changes: 1 addition & 1 deletion artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -417,7 +417,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=128, ififo_depth=128))

self.config["RTIO_FIRST_PHASER_CHANNEL"] = len(rtio_channels)
self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]
self.submodules += sawgs

23 changes: 23 additions & 0 deletions doc/manual/core_device.rst
Original file line number Diff line number Diff line change
@@ -151,6 +151,29 @@ See :mod:`artiq.coredevice.i2c` for more details.

For safe operation of the DDS buses (to prevent damage to the IO banks of the FPGA), the FMC VADJ rail of the KC705 should be changed to 3.3V. Plug the Texas Instruments USB-TO-GPIO PMBus adapter into the PMBus connector in the corner of the KC705 and use the Fusion Digital Power Designer software to configure (requires Windows). Write to chip number U55 (address 52), channel 4, which is the VADJ rail, to make it 3.3V instead of 2.5V. Power cycle the KC705 board to check that the startup voltage on the VADJ rail is now 3.3V.

Phaser
++++++

The Phaser adapter is an AD9154-FMC-EBZ, a 4 channel 2.4 GHz DAC on an FMC HPC card.

+--------------+------------+--------------+
| RTIO channel | TTL line | Capability |
+==============+============+==============+
| 0 | SMA_GPIO_N | Input+Output |
+--------------+------------+--------------+
| 1 | LED | Output |
+--------------+------------+--------------+

The board has RTIO SPI buses mapped as follows:

+--------------+-------------+-------------+-----------+------------+
| RTIO channel | CS_N | MOSI | MISO | CLK |
+==============+=============+=============+===========+============+
| 2 | DAC_CS_N | DAC_MOSI | DAC_MISO | DAC_CLK |
+--------------+-------------+-------------+-----------+------------+

The SAWG channels start with RTIO channel number 3.

Pipistrello
-----------

6 changes: 6 additions & 0 deletions doc/manual/core_drivers_reference.rst
Original file line number Diff line number Diff line change
@@ -53,3 +53,9 @@ These drivers are for the core device and the peripherals closely integrated int

.. automodule:: artiq.coredevice.exceptions
:members:

:mod:`artiq.coredevice.sawg` module
-----------------------------------

.. automodule:: artiq.coredevice.sawg
:members: