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| 1 | +#ifndef __AD9516_REG_H |
| 2 | +#define __AD9516_REG_H |
| 3 | + |
| 4 | +#define AD9516_SERIAL_PORT_CONFIGURATION 0x000 |
| 5 | +#define AD9516_SDO_ACTIVE (1 << 0) /* 1, 0x00 R/W */ |
| 6 | +#define AD9516_LSB_FIRST (1 << 1) /* 1, 0x00 R/W */ |
| 7 | +#define AD9516_SOFT_RESET (1 << 2) /* 1, 0x00 R/W */ |
| 8 | +#define AD9516_LONG_INSTRUCTION (1 << 3) /* 1, 0x01 R/W */ |
| 9 | +#define AD9516_LONG_INSTRUCTION_MIRRORED (1 << 4) /* 1, 0x01 R/W */ |
| 10 | +#define AD9516_SOFT_RESET_MIRRORED (1 << 5) /* 1, 0x00 R/W */ |
| 11 | +#define AD9516_LSB_FIRST_MIRRORED (1 << 6) /* 1, 0x00 R/W */ |
| 12 | +#define AD9516_SDO_ACTIVE_MIRRORED (1 << 7) /* 1, 0x00 R/W */ |
| 13 | + |
| 14 | +#define AD9516_PART_ID 0x003 |
| 15 | + |
| 16 | +#define AD9516_READBACK_CONTROL 0x004 |
| 17 | +#define AD9516_READ_BACK_ACTIVE_REGISTERS (1 << 0) /* 1, 0x00 R/W */ |
| 18 | + |
| 19 | +#define AD9516_PFD_AND_CHARGE_PUMP 0x010 |
| 20 | +#define AD9516_PLL_POWER_DOWN (1 << 0) /* 2, 0x01 R/W */ |
| 21 | +#define AD9516_CHARGE_PUMP_MODE (1 << 2) /* 2, 0x03 R/W */ |
| 22 | +#define AD9516_CHARGE_PUMP_CURRENT (1 << 4) /* 3, 0x07 R/W */ |
| 23 | +#define AD9516_PFD_POLARITY (1 << 7) /* 1, 0x00 R/W */ |
| 24 | + |
| 25 | +#define AD9516_R_COUNTER_LSB 0x011 |
| 26 | +#define AD9516_R_COUNTER_MSB 0x012 |
| 27 | + |
| 28 | +#define AD9516_A_COUNTER 0x013 |
| 29 | + |
| 30 | +#define AD9516_B_COUNTER_LSB 0x014 |
| 31 | +#define AD9516_B_COUNTER_LSB 0x015 |
| 32 | + |
| 33 | +#define AD9516_PLL_CONTROL_1 0x016 |
| 34 | +#define AD9516_PRESCALER_P (1 << 0) /* 3, 0x06 R/W */ |
| 35 | +#define AD9516_B_COUNTER_BYPASS (1 << 3) /* 1, 0x00 R/W */ |
| 36 | +#define AD9516_RESET_ALL_COUNTERS (1 << 4) /* 1, 0x00 R/W */ |
| 37 | +#define AD9516_RESET_A_AND_B_COUNTERS (1 << 5) /* 1, 0x00 R/W */ |
| 38 | +#define AD9516_RESET_R_COUNTER (1 << 6) /* 1, 0x00 R/W */ |
| 39 | +#define AD9516_SET_CP_PIN_TO_VCP_2 (1 << 7) /* 1, 0x00 R/W */ |
| 40 | + |
| 41 | +#define AD9516_PLL_CONTROL_2 0x017 |
| 42 | +#define AD9516_ANTIBACKLASH_PULSE_WIDTH (1 << 0) /* 2, 0x00 R/W */ |
| 43 | +#define AD9516_STATUS_PIN_CONTROL (1 << 2) /* 6, 0x00 R/W */ |
| 44 | + |
| 45 | +#define AD9516_PLL_CONTROL_3 0x018 |
| 46 | +#define AD9516_VCO_CAL_NOW (1 << 0) /* 1, 0x00 R/W */ |
| 47 | +#define AD9516_VCO_CALIBRATION_DIVIDER (1 << 1) /* 2, 0x03 R/W */ |
| 48 | +#define AD9516_DISABLE_DIGITAL_LOCK_DETECT (1 << 3) /* 1, 0x00 R/W */ |
| 49 | +#define AD9516_DIGITAL_LOCK_DETECT_WINDOW (1 << 4) /* 1, 0x00 R/W */ |
| 50 | +#define AD9516_LOCK_DETECT_COUNTER (1 << 5) /* 2, 0x00 R/W */ |
| 51 | + |
| 52 | +#define AD9516_PLL_CONTROL_4 0x019 |
| 53 | +#define AD9516_N_PATH_DELAY (1 << 0) /* 3, 0x00 R/W */ |
| 54 | +#define AD9516_R_PATH_DELAY (1 << 3) /* 3, 0x00 R/W */ |
| 55 | +#define AD9516_R_A_B_COUNTERS_SYNC_PIN_RESET (1 << 6) /* 2, 0x00 R/W */ |
| 56 | + |
| 57 | +#define AD9516_PLL_CONTROL_5 0x01a |
| 58 | +#define AD9516_LD_PIN_CONTROL (1 << 0) /* 6, 0x00 R/W */ |
| 59 | +#define AD9516_REFERENCE_FREQUENCY_MONITOR_THRESHOLD (1 << 6) /* 1, 0x00 R/W */ |
| 60 | + |
| 61 | +#define AD9516_PLL_CONTROL_6 0x01b |
| 62 | +#define AD9516_REFMON_PIN_CONTROL (1 << 0) /* 5, 0x00 R/W */ |
| 63 | +#define AD9516_REF1_REFIN_FREQUENCY_MONITOR (1 << 5) /* 1, 0x00 R/W */ |
| 64 | +#define AD9516_REF2_REFIN_FREQUENCY_MONITOR (1 << 6) /* 1, 0x00 R/W */ |
| 65 | +#define AD9516_VCO_FREQUENCY_MONITOR (1 << 7) /* 1, 0x00 R/W */ |
| 66 | + |
| 67 | +#define AD9516_PLL_CONTROL_7 0x01c |
| 68 | +#define AD9516_DIFFERENTIAL_REFERENCE (1 << 0) /* 1, 0x00 R/W */ |
| 69 | +#define AD9516_REF1_POWER_ON (1 << 1) /* 1, 0x00 R/W */ |
| 70 | +#define AD9516_REF2_POWER_ON (1 << 2) /* 1, 0x00 R/W */ |
| 71 | +#define AD9516_USE_REF_SEL_PIN (1 << 5) /* 1, 0x00 R/W */ |
| 72 | +#define AD9516_SELECT_REF2 (1 << 6) /* 1, 0x00 R/W */ |
| 73 | +#define AD9516_DISABLE_SWITCHOVER_DEGLITCH (1 << 7) /* 1, 0x00 R/W */ |
| 74 | + |
| 75 | +#define AD9516_PLL_CONTROL_8 0x01d |
| 76 | +#define AD9516_HOLDOVER_ENABLE (1 << 0) /* 1, 0x00 R/W */ |
| 77 | +#define AD9516_EXTERNAL_HOLDOVER_CONTROL (1 << 1) /* 1, 0x00 R/W */ |
| 78 | +#define AD9516_HOLDOVER_ENABLEreg001D (1 << 2) /* 1, 0x00 R/W */ |
| 79 | +#define AD9516_LD_PIN_COMPARATOR_ENABLE (1 << 3) /* 1, 0x00 R/W */ |
| 80 | +#define AD9516_PLL_STATUS_REGISTER_DISABLE (1 << 4) /* 1, 0x00 R/W */ |
| 81 | + |
| 82 | +#define AD9516_PLL_READBACK 0x01f |
| 83 | +#define AD9516_DIGITAL_LOCK_DETECT (1 << 0) /* 1, 0x00 R */ |
| 84 | +#define AD9516_REF1_FREQUENCY_THRESHOLD (1 << 1) /* 1, 0x00 R */ |
| 85 | +#define AD9516_REF2_FREQUENCY_THRESHOLD (1 << 2) /* 1, 0x00 R */ |
| 86 | +#define AD9516_VCO_FREQUENCY_THRESHOLD (1 << 3) /* 1, 0x00 R */ |
| 87 | +#define AD9516_REF2_SELECTED (1 << 4) /* 1, 0x00 R */ |
| 88 | +#define AD9516_HOLDOVER_ACTIVE (1 << 5) /* 1, 0x00 R */ |
| 89 | +#define AD9516_VCO_CAL_FINISHED (1 << 6) /* 1, 0x00 R */ |
| 90 | + |
| 91 | +#define AD9516_OUT6_DELAY_BYPASS 0x0a0 |
| 92 | + |
| 93 | +#define AD9516_OUT6_DELAY_FULL_SCALE 0x0a1 |
| 94 | +#define AD9516_OUT6_RAMP_CURRENT (1 << 0) /* 3, 0x00 R/W */ |
| 95 | +#define AD9516_OUT6_RAMP_CAPACITORS (1 << 3) /* 3, 0x00 R/W */ |
| 96 | + |
| 97 | +#define AD9516_OUT6_DELAY_FRACTION 0x0a2 |
| 98 | + |
| 99 | +#define AD9516_OUT7_DELAY_BYPASS 0x0a3 |
| 100 | + |
| 101 | +#define AD9516_OUT7_DELAY_FULL_SCALE 0x0a4 |
| 102 | +#define AD9516_OUT7_RAMP_CURRENT (1 << 0) /* 3, 0x00 R/W */ |
| 103 | +#define AD9516_OUT7_RAMP_CAPACITORS (1 << 3) /* 3, 0x00 R/W */ |
| 104 | + |
| 105 | +#define AD9516_OUT7_DELAY_FRACTION 0x0a5 |
| 106 | + |
| 107 | +#define AD9516_OUT8_DELAY_BYPASS 0x0a6 |
| 108 | + |
| 109 | +#define AD9516_OUT8_DELAY_FULL_SCALE 0x0a7 |
| 110 | +#define AD9516_OUT8_RAMP_CURRENT (1 << 0) /* 3, 0x00 R/W */ |
| 111 | +#define AD9516_OUT8_RAMP_CAPACITORS (1 << 3) /* 3, 0x00 R/W */ |
| 112 | + |
| 113 | +#define AD9516_OUT8_DELAY_FRACTION 0x0a8 |
| 114 | + |
| 115 | +#define AD9516_OUT9_DELAY_BYPASS 0x0a9 |
| 116 | + |
| 117 | +#define AD9516_OUT9_DELAY_FULL_SCALE 0x0aa |
| 118 | +#define AD9516_OUT9_RAMP_CURRENT (1 << 0) /* 3, 0x00 R/W */ |
| 119 | +#define AD9516_OUT9_RAMP_CAPACITORS (1 << 3) /* 3, 0x00 R/W */ |
| 120 | + |
| 121 | +#define AD9516_OUT9_DELAY_FRACTION 0x0ab |
| 122 | + |
| 123 | +#define AD9516_OUT0 0x0f0 |
| 124 | +#define AD9516_OUT0_POWER_DOWN (1 << 0) /* 2, 0x00 R/W */ |
| 125 | +#define AD9516_OUT0_LVPECL_DIFFERENTIAL_VOLTAGE (1 << 2) /* 2, 0x02 R/W */ |
| 126 | +#define AD9516_OUT0_INVERT (1 << 4) /* 1, 0x00 R/W */ |
| 127 | + |
| 128 | +#define AD9516_OUT1 0x0f1 |
| 129 | +#define AD9516_OUT1_POWER_DOWN (1 << 0) /* 2, 0x02 R/W */ |
| 130 | +#define AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE (1 << 2) /* 2, 0x02 R/W */ |
| 131 | +#define AD9516_OUT1_INVERT (1 << 4) /* 1, 0x00 R/W */ |
| 132 | + |
| 133 | +#define AD9516_OUT2 0x0f2 |
| 134 | +#define AD9516_OUT2_POWER_DOWN (1 << 0) /* 2, 0x00 R/W */ |
| 135 | +#define AD9516_OUT2_LVPECL_DIFFERENTIAL_VOLTAGE (1 << 2) /* 2, 0x02 R/W */ |
| 136 | +#define AD9516_OUT2_INVERT (1 << 4) /* 1, 0x00 R/W */ |
| 137 | + |
| 138 | +#define AD9516_OUT3 0x0f3 |
| 139 | +#define AD9516_OUT3_POWER_DOWN (1 << 0) /* 2, 0x02 R/W */ |
| 140 | +#define AD9516_OUT3_LVPECL_DIFFERENTIAL_VOLTAGE (1 << 2) /* 2, 0x02 R/W */ |
| 141 | +#define AD9516_OUT3_INVERT (1 << 4) /* 1, 0x00 R/W */ |
| 142 | + |
| 143 | +#define AD9516_OUT4 0x0f4 |
| 144 | +#define AD9516_OUT4_POWER_DOWN (1 << 0) /* 2, 0x02 R/W */ |
| 145 | +#define AD9516_OUT4_LVPECL_DIFFERENTIAL_VOLTAGE (1 << 2) /* 2, 0x02 R/W */ |
| 146 | +#define AD9516_OUT4_INVERT (1 << 4) /* 1, 0x00 R/W */ |
| 147 | + |
| 148 | +#define AD9516_OUT5 0x0f5 |
| 149 | +#define AD9516_OUT5_POWER_DOWN (1 << 0) /* 2, 0x02 R/W */ |
| 150 | +#define AD9516_OUT5_LVPECL_DIFFERENTIAL_VOLTAGE (1 << 2) /* 2, 0x02 R/W */ |
| 151 | +#define AD9516_OUT5_INVERT (1 << 4) /* 1, 0x00 R/W */ |
| 152 | + |
| 153 | +#define AD9516_OUT6 0x140 |
| 154 | +#define AD9516_OUT6_POWER_DOWN (1 << 0) /* 1, 0x00 R/W */ |
| 155 | +#define AD9516_OUT6_LVDS_OUTPUT_CURRENT (1 << 1) /* 2, 0x01 R/W */ |
| 156 | +#define AD9516_OUT6_SELECT_LVDS_CMOS (1 << 3) /* 1, 0x00 R/W */ |
| 157 | +#define AD9516_OUT6_CMOS_B (1 << 4) /* 1, 0x00 R/W */ |
| 158 | +#define AD9516_OUT6_LVDS_CMOS_OUTPUT_POLARITY (1 << 5) /* 1, 0x00 R/W */ |
| 159 | +#define AD9516_OUT6_CMOS_OUTPUT_POLARITY (1 << 6) /* 2, 0x01 R/W */ |
| 160 | + |
| 161 | +#define AD9516_OUT7 0x141 |
| 162 | +#define AD9516_OUT7_POWER_DOWN (1 << 0) /* 1, 0x01 R/W */ |
| 163 | +#define AD9516_OUT7_LVDS_OUTPUT_CURRENT (1 << 1) /* 2, 0x01 R/W */ |
| 164 | +#define AD9516_OUT7_SELECT_LVDS_CMOS (1 << 3) /* 1, 0x00 R/W */ |
| 165 | +#define AD9516_OUT7_CMOS_B (1 << 4) /* 1, 0x00 R/W */ |
| 166 | +#define AD9516_OUT7_LVDS__CMOS_OUTPUT_POLARITY (1 << 5) /* 1, 0x00 R/W */ |
| 167 | +#define AD9516_OUT7_CMOS_OUTPUT_POLARITY (1 << 6) /* 2, 0x01 R/W */ |
| 168 | + |
| 169 | +#define AD9516_OUT8 0x142 |
| 170 | +#define AD9516_OUT8_POWER_DOWN (1 << 0) /* 1, 0x00 R/W */ |
| 171 | +#define AD9516_OUT8_LVDS_OUTPUT_CURRENT (1 << 1) /* 2, 0x01 R/W */ |
| 172 | +#define AD9516_OUT8_SELECT_LVDS_CMOS (1 << 3) /* 1, 0x00 R/W */ |
| 173 | +#define AD9516_OUT8_CMOS_B (1 << 4) /* 1, 0x00 R/W */ |
| 174 | +#define AD9516_OUT8_LVDS_CMOS_OUTPUT_POLARITY (1 << 5) /* 1, 0x00 R/W */ |
| 175 | +#define AD9516_OUT8_CMOS_OUTPUT_POLARITY (1 << 6) /* 2, 0x01 R/W */ |
| 176 | + |
| 177 | +#define AD9516_OUT9 0x143 |
| 178 | +#define AD9516_OUT9_POWER_DOWN (1 << 0) /* 1, 0x01 R/W */ |
| 179 | +#define AD9516_OUT9_LVDS_OUTPUT_CURRENT (1 << 1) /* 2, 0x01 R/W */ |
| 180 | +#define AD9516_OUT9_SELECT_LVDS_CMOS (1 << 3) /* 1, 0x00 R/W */ |
| 181 | +#define AD9516_OUT9_CMOS_B (1 << 4) /* 1, 0x00 R/W */ |
| 182 | +#define AD9516_OUT9_LVDS__CMOS_OUTPUT_POLARITY (1 << 5) /* 1, 0x00 R/W */ |
| 183 | +#define AD9516_OUT9_CMOS_OUTPUT_POLARITY (1 << 6) /* 2, 0x01 R/W */ |
| 184 | + |
| 185 | +#define AD9516_DIVIDER_0_0 0x190 |
| 186 | +#define AD9516_DIVIDER_0_HIGH_CYCLES (1 << 0) /* 4, 0x00 R/W */ |
| 187 | +#define AD9516_DIVIDER_0_LOW_CYCLES (1 << 4) /* 4, 0x00 R/W */ |
| 188 | + |
| 189 | +#define AD9516_DIVIDER_0_1 0x191 |
| 190 | +#define AD9516_DIVIDER_0_PHASE_OFFSET (1 << 0) /* 4, 0x00 R/W */ |
| 191 | +#define AD9516_DIVIDER_0_START_HIGH (1 << 4) /* 1, 0x00 R/W */ |
| 192 | +#define AD9516_DIVIDER_0_FORCE_HIGH (1 << 5) /* 1, 0x00 R/W */ |
| 193 | +#define AD9516_DIVIDER_0_NOSYNC (1 << 6) /* 1, 0x00 R/W */ |
| 194 | +#define AD9516_DIVIDER_0_BYPASS (1 << 7) /* 1, 0x01 R/W */ |
| 195 | + |
| 196 | +#define AD9516_DIVIDER_0_2 0x192 |
| 197 | +#define AD9516_DIVIDER_0_DCCOFF (1 << 0) /* 1, 0x00 R/W */ |
| 198 | +#define AD9516_DIVIDER_0_DIRECT_TO_OUTPUT (1 << 1) /* 1, 0x00 R/W */ |
| 199 | + |
| 200 | +#define AD9516_DIVIDER_1_0 0x193 |
| 201 | +#define AD9516_DIVIDER_1_HIGH_CYCLES (1 << 0) /* 4, 0x00 R/W */ |
| 202 | +#define AD9516_DIVIDER_1_LOW_CYCLES (1 << 4) /* 4, 0x00 R/W */ |
| 203 | + |
| 204 | +#define AD9516_DIVIDER_1_1 0x194 |
| 205 | +#define AD9516_DIVIDER_1_PHASE_OFFSET (1 << 0) /* 4, 0x00 R/W */ |
| 206 | +#define AD9516_DIVIDER_1_START_HIGH (1 << 4) /* 1, 0x00 R/W */ |
| 207 | +#define AD9516_DIVIDER_1_FORCE_HIGH (1 << 5) /* 1, 0x00 R/W */ |
| 208 | +#define AD9516_DIVIDER_1_NOSYNC (1 << 6) /* 1, 0x00 R/W */ |
| 209 | +#define AD9516_DIVIDER_1_BYPASS (1 << 7) /* 1, 0x00 R/W */ |
| 210 | + |
| 211 | +#define AD9516_DIVIDER_1_2 0x195 |
| 212 | +#define AD9516_DIVIDER_1_DCCOFF (1 << 0) /* 1, 0x00 R/W */ |
| 213 | +#define AD9516_DIVIDER_1_DIRECT_TO_OUTPUT (1 << 1) /* 1, 0x00 R/W */ |
| 214 | + |
| 215 | +#define AD9516_DIVIDER_2_0 0x196 |
| 216 | +#define AD9516_DIVIDER_2_HIGH_CYCLES (1 << 0) /* 4, 0x00 R/W */ |
| 217 | +#define AD9516_DIVIDER_2_LOW_CYCLES (1 << 4) /* 4, 0x00 R/W */ |
| 218 | + |
| 219 | +#define AD9516_DIVIDER_2_1 0x197 |
| 220 | +#define AD9516_DIVIDER_2_PHASE_OFFSET (1 << 0) /* 4, 0x00 R/W */ |
| 221 | +#define AD9516_DIVIDER_2_START_HIGH (1 << 4) /* 1, 0x00 R/W */ |
| 222 | +#define AD9516_DIVIDER_2_FORCE_HIGH (1 << 5) /* 1, 0x00 R/W */ |
| 223 | +#define AD9516_DIVIDER_2_NOSYNC (1 << 6) /* 1, 0x00 R/W */ |
| 224 | +#define AD9516_DIVIDER_2_BYPASS (1 << 7) /* 1, 0x00 R/W */ |
| 225 | + |
| 226 | +#define AD9516_DIVIDER_2_2 0x198 |
| 227 | +#define AD9516_DIVIDER_2_DCCOFF (1 << 0) /* 1, 0x00 R/W */ |
| 228 | +#define AD9516_DIVIDER_2_DIRECT_TO_OUTPUT (1 << 1) /* 1, 0x00 R/W */ |
| 229 | + |
| 230 | +#define AD9516_DIVIDER_3_0 0x199 |
| 231 | +#define AD9516_DIVIDER_3_HIGH_CYCLES_1 (1 << 0) /* 4, 0x02 R/W */ |
| 232 | +#define AD9516_DIVIDER_3_LOW_CYCLES_1 (1 << 4) /* 4, 0x02 R/W */ |
| 233 | + |
| 234 | +#define AD9516_DIVIDER_3_1 0x19a |
| 235 | +#define AD9516_DIVIDER_3_PHASE_OFFSET_1 (1 << 0) /* 4, 0x00 R/W */ |
| 236 | +#define AD9516_DIVIDER_3_PHASE_OFFSET_2 (1 << 4) /* 4, 0x00 R/W */ |
| 237 | + |
| 238 | +#define AD9516_DIVIDER_3_2 0x19b |
| 239 | +#define AD9516_DIVIDER_3_HIGH_CYCLES_2 (1 << 0) /* 4, 0x01 R/W */ |
| 240 | +#define AD9516_DIVIDER_3_LOW_CYCLES_2 (1 << 4) /* 4, 0x01 R/W */ |
| 241 | + |
| 242 | +#define AD9516_DIVIDER_3_3 0x19c |
| 243 | +#define AD9516_DIVIDER_3_START_HIGH_1 (1 << 0) /* 1, 0x00 R/W */ |
| 244 | +#define AD9516_DIVIDER_3_START_HIGH_2 (1 << 1) /* 1, 0x00 R/W */ |
| 245 | +#define AD9516_DIVIDER_3_FORCE_HIGH (1 << 2) /* 1, 0x00 R/W */ |
| 246 | +#define AD9516_DIVIDER_3_NOSYNC (1 << 3) /* 1, 0x00 R/W */ |
| 247 | +#define AD9516_DIVIDER_3_BYPASS_1 (1 << 4) /* 1, 0x00 R/W */ |
| 248 | +#define AD9516_DIVIDER_3_BYPASS_2 (1 << 5) /* 1, 0x00 R/W */ |
| 249 | + |
| 250 | +#define AD9516_DIVIDER_3_4 0x19d |
| 251 | +#define AD9516_DIVIDER_3_DCCOFF (1 << 0) /* 1, 0x00 R/W */ |
| 252 | + |
| 253 | +#define AD9516_DIVIDER_4_0 0x19e |
| 254 | +#define AD9516_DIVIDER_4_HIGH_CYCLES_1 (1 << 0) /* 4, 0x02 R/W */ |
| 255 | +#define AD9516_DIVIDER_4_LOW_CYCLES_1 (1 << 4) /* 4, 0x02 R/W */ |
| 256 | + |
| 257 | +#define AD9516_DIVIDER_4_1 0x19f |
| 258 | +#define AD9516_DIVIDER_4_PHASE_OFFSET_1 (1 << 0) /* 4, 0x00 R/W */ |
| 259 | +#define AD9516_DIVIDER_4_PHASE_OFFSET_2 (1 << 4) /* 4, 0x00 R/W */ |
| 260 | + |
| 261 | +#define AD9516_DIVIDER_4_2 0x1a0 |
| 262 | +#define AD9516_DIVIDER_4_HIGH_CYCLES_2 (1 << 0) /* 4, 0x01 R/W */ |
| 263 | +#define AD9516_DIVIDER_4_LOW_CYCLES_2 (1 << 4) /* 4, 0x01 R/W */ |
| 264 | + |
| 265 | +#define AD9516_DIVIDER_4_3 0x1a1 |
| 266 | +#define AD9516_DIVIDER_4_START_HIGH_1 (1 << 0) /* 1, 0x00 R/W */ |
| 267 | +#define AD9516_DIVIDER_4_START_HIGH_2 (1 << 1) /* 1, 0x00 R/W */ |
| 268 | +#define AD9516_DIVIDER_4_FORCE_HIGH (1 << 2) /* 1, 0x00 R/W */ |
| 269 | +#define AD9516_DIVIDER_4_NOSYNC (1 << 3) /* 1, 0x00 R/W */ |
| 270 | +#define AD9516_DIVIDER_4_BYPASS_1 (1 << 4) /* 1, 0x00 R/W */ |
| 271 | +#define AD9516_DIVIDER_4_BYPASS_2 (1 << 5) /* 1, 0x00 R/W */ |
| 272 | + |
| 273 | +#define AD9516_DIVIDER_4_4 0x1a2 |
| 274 | +#define AD9516_DIVIDER_4_DCCOFF (1 << 0) /* 1, 0x00 R/W */ |
| 275 | + |
| 276 | +#define AD9516_VCO_DIVIDER 0x1e0 |
| 277 | + |
| 278 | +#define AD9516_INPUT_CLKS 0x1e1 |
| 279 | +#define AD9516_BYPASS_VCO_DIVIDER (1 << 0) /* 1, 0x00 R/W */ |
| 280 | +#define AD9516_SELECT_VCO_OR_CLK (1 << 1) /* 1, 0x00 R/W */ |
| 281 | +#define AD9516_POWER_DOWN_VCO_AND_CLK (1 << 2) /* 1, 0x00 R/W */ |
| 282 | +#define AD9516_POWER_DOWN_VCO_CLOCK_INTERFACE (1 << 3) /* 1, 0x00 R/W */ |
| 283 | +#define AD9516_POWER_DOWN_CLOCK_INPUT_SECTION (1 << 4) /* 1, 0x00 R/W */ |
| 284 | + |
| 285 | +#define AD9516_POWER_DOWN_AND_SYNC 0x230 |
| 286 | +#define AD9516_SOFT_SYNC (1 << 0) /* 1, 0x00 R/W */ |
| 287 | +#define AD9516_POWER_DOWN_DISTRIBUTION_REFERENCE (1 << 1) /* 1, 0x00 R/W */ |
| 288 | +#define AD9516_POWER_DOWN_SYNC (1 << 2) /* 1, 0x00 R/W */ |
| 289 | + |
| 290 | +#define AD9516_UPDATE_ALL_REGISTERS 0x232 |
| 291 | + |
| 292 | +#endif |
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