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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 09f46dab7087
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  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Sep 3, 2016

  1. examples/phaser: typo

    jordens committed Sep 3, 2016
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    b64a1b2 View commit details
  2. Copy the full SHA
    09f46da View commit details
Showing with 17 additions and 23 deletions.
  1. +4 −4 artiq/examples/phaser/repository/sawg.py
  2. +3 −3 artiq/gateware/dsp/sawg.py
  3. +2 −3 artiq/gateware/dsp/test_accu.py
  4. +8 −13 artiq/gateware/dsp/test_sawg.py
8 changes: 4 additions & 4 deletions artiq/examples/phaser/repository/sawg.py
Original file line number Diff line number Diff line change
@@ -21,10 +21,10 @@ def run(self):
self.sawg1.set_amplitude(-1)
self.sawg2.set_amplitude(.5)
self.sawg3.set_amplitude(.5)
self.sawg0.set_frequency(1*Mhz)
self.sawg1.set_frequency(100*Mhz)
self.sawg2.set_frequency(200*Mhz)
self.sawg3.set_frequency(200*Mhz)
self.sawg0.set_frequency(1*MHz)
self.sawg1.set_frequency(100*MHz)
self.sawg2.set_frequency(200*MHz)
self.sawg3.set_frequency(200*MHz)
self.sawg0.set_phase(0)
self.sawg1.set_phase(0)
self.sawg2.set_phase(0)
6 changes: 3 additions & 3 deletions artiq/gateware/dsp/sawg.py
Original file line number Diff line number Diff line change
@@ -15,7 +15,7 @@ def __init__(self, width, parallelism=4):
self.o = [Signal((width, True)) for i in range(parallelism)]

self.parallelism = parallelism
self.latency = 0 # will be accumulated
self.latency = 1 # will be accumulated

q = PhasedAccu(width, parallelism)
self.submodules += q
@@ -38,15 +38,15 @@ def __init__(self, width, parallelism=4):
),
If(self.p.stb,
eqh(q.i.p, self.p.p)
)
),
q.i.stb.eq(self.f.stb | self.p.stb),
]
self.comb += [
self.a.ack.eq(1),
self.f.ack.eq(1),
self.p.ack.eq(1),
q.o.ack.eq(1),
q.i.clr.eq(0),
q.i.stb.eq(self.f.stb | self.p.stb),
]

c = []
5 changes: 2 additions & 3 deletions artiq/gateware/dsp/test_accu.py
Original file line number Diff line number Diff line change
@@ -3,9 +3,8 @@
from migen import *
from migen.fhdl.verilog import convert

from accu import Accu, PhasedAccu

from tools import xfer
from artiq.gateware.dsp.accu import Accu, PhasedAccu
from artiq.gateware.dsp.tools import xfer


def read(o, n):
21 changes: 8 additions & 13 deletions artiq/gateware/dsp/test_sawg.py
Original file line number Diff line number Diff line change
@@ -3,36 +3,31 @@
from migen import *
from migen.fhdl.verilog import convert

from sawg import DDS

from tools import xfer
from artiq.gateware.dsp.sawg import DDSFast
from artiq.gateware.dsp.tools import xfer


def _test_gen_dds(dut, o):
yield dut.ce.eq(1)
yield dut.clr.eq(1)
yield from xfer(dut,
a1=dict(a0=10),
p1=dict(a0=0),
f1=dict(a0=0 << 16, a1=0),
f=dict(a0=10 << 24),
p=dict(a0=0),
a=dict(a=10),
p=dict(p=0),
f=dict(f=1 << 16),
)
for i in range(256):
yield
o.append((yield from [((yield _[0]), (yield _[1])) for _ in dut.o]))
o.append((yield from [(yield _) for _ in dut.o]))


def _test_channel():
dut = DDS(width=8, parallelism=2)
dut = DDSFast(width=8, parallelism=2)

if False:
print(convert(dut))
else:
o = []
run_simulation(dut, _test_gen_dds(dut, o), vcd_name="dds.vcd")
o = np.array(o)
print(o[:, :, 0])
print(o[:, :])


if __name__ == "__main__":