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phaser: non-rtio spi
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jordens committed Sep 4, 2016
1 parent 1feb7cf commit 71bd2d9
Showing 3 changed files with 16 additions and 17 deletions.
14 changes: 4 additions & 10 deletions artiq/examples/phaser/device_db.pyon
Original file line number Diff line number Diff line change
@@ -30,34 +30,28 @@
"class": "TTLOut",
"arguments": {"channel": 1}
},
"dac0_spi": {
"type": "local",
"module": "artiq.coredevice.spi",
"class": "SPIMaster",
"arguments": {"channel": 2}
},
"sawg0": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 3, "parallelism": 4}
"arguments": {"channel_base": 2, "parallelism": 4}
},
"sawg1": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 6, "parallelism": 4}
"arguments": {"channel_base": 5, "parallelism": 4}
},
"sawg2": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 9, "parallelism": 4}
"arguments": {"channel_base": 8, "parallelism": 4}
},
"sawg3": {
"type": "local",
"module": "artiq.coredevice.sawg",
"class": "SAWG",
"arguments": {"channel_base": 12, "parallelism": 4}
"arguments": {"channel_base": 11, "parallelism": 4}
}
}
1 change: 0 additions & 1 deletion artiq/examples/phaser/repository/sawg.py
Original file line number Diff line number Diff line change
@@ -6,7 +6,6 @@ def build(self):
self.setattr_device("core")
self.setattr_device("led")

self.setattr_device("dac0_spi")
self.setattr_device("sawg0")
self.setattr_device("sawg1")
self.setattr_device("sawg2")
18 changes: 12 additions & 6 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -13,6 +13,7 @@
from misoc.interconnect.csr import *
from misoc.interconnect import wishbone
from misoc.cores import gpio
from misoc.cores import spi as spi_csr
from misoc.integration.soc_core import mem_decoder
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
from misoc.integration.builder import builder_args, builder_argdict
@@ -390,6 +391,13 @@ def __init__(self, cpu_type="or1k", **kwargs):


class Phaser(_NIST_Ions):
csr_map = {}
csr_map.update(_NIST_Ions.csr_map)
csr_map["spi_fmc_hpc"] = None
mem_map = {}
mem_map.update(_NIST_Ions.mem_map)
mem_map["spi_fmc_hpc"] = 0x40000000 # (shadow @0xc0000000)

def __init__(self, cpu_type="or1k", **kwargs):
_NIST_Ions.__init__(self, cpu_type, **kwargs)

@@ -410,12 +418,10 @@ def __init__(self, cpu_type="or1k", **kwargs):

self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)

self.config["RTIO_FIRST_SPI_CHANNEL"] = len(rtio_channels)
# TODO: dummy, hookup ad9154 spi here
phy = spi.SPIMaster(self.platform.request("spi", 0))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(
phy, ofifo_depth=128, ififo_depth=128))
# TODO: dummy, hookup actual fmc hpc spi here
self.submodules.spi_fmc_hpc = spi_csr.SPIMaster(
self.platform.request("spi", 0))
self.register_kernel_cpu_csrdevice("spi_fmc_hpc")

self.config["RTIO_FIRST_SAWG_CHANNEL"] = len(rtio_channels)
sawgs = [sawg.Channel(width=16, parallelism=4) for i in range(4)]

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