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base repository: m-labs/misoc
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head repository: m-labs/misoc
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compare: f6e4882b3136
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  • 2 commits
  • 4 files changed
  • 1 contributor

Commits on Sep 24, 2016

  1. Copy the full SHA
    cd95af4 View commit details
  2. add TMPU

    sbourdeauducq committed Sep 24, 2016
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    f6e4882 View commit details
Showing with 73 additions and 2 deletions.
  1. +60 −0 misoc/cores/tmpu.py
  2. +4 −2 misoc/integration/soc_core.py
  3. +5 −0 misoc/interconnect/csr_bus.py
  4. +4 −0 misoc/interconnect/wishbone.py
60 changes: 60 additions & 0 deletions misoc/cores/tmpu.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,60 @@
"""
Trivial memory protection unit.
Memory is divided into "pages" of 2**page_bits words.
Bus errors are generated in two cases:
* accesses within page 0 (to help catch NULL pointers dereferences)
* accesses within a programmable page (to implement stack probing)
To avoid a delay of one cycle, the transaction is sent immediately to the
output bus. Thus, bus cycles are not aborted, in particular write transactions
will be executed even if they trigger the protection. Stack probing should use
read transactions for this reason.
This module must not be used with Wishbone combinatorial feedback (slaves may
not ack transactions in the same cycle as they are issued).
All sizes/addresses in bytes.
"""

from migen import *

from misoc.interconnect import wishbone
from misoc.interconnect.csr import *


class TMPU(Module, AutoCSR):
def __init__(self, input_bus, page_size=4096):
self.output_bus = wishbone.Interface.like(input_bus)

word_bits = log2_int(len(input_bus.dat_w)//8)
page_bits = log2_int(page_size//8) - word_bits

self.page_size = CSRConstant(2**(word_bits+page_bits))
self.enable_null = CSRStorage()
self.enable_prog = CSRStorage()
self.prog_address = CSRStorage(len(input_bus.adr),
alignment_bits=word_bits+page_bits)

# # #

error = Signal()
page = input_bus.adr[page_bits:]
self.sync += [
error.eq(0),
If(self.enable_null.storage &
(page == 0), error.eq(1)),
If(self.enable_prog.storage &
(page == self.prog_address.storage), error.eq(1))
]
self.comb += [
input_bus.connect(self.output_bus, leave_out={"ack", "err"}),
If(error,
input_bus.ack.eq(0),
input_bus.err.eq(self.output_bus.ack | self.output_bus.err)
).Else(
input_bus.ack.eq(self.output_bus.ack),
input_bus.err.eq(self.output_bus.err)
)
]
6 changes: 4 additions & 2 deletions misoc/integration/soc_core.py
Original file line number Diff line number Diff line change
@@ -2,7 +2,7 @@

from migen import *

from misoc.cores import lm32, mor1kx, identifier, timer, uart
from misoc.cores import lm32, mor1kx, tmpu, identifier, timer, uart
from misoc.interconnect import wishbone, csr_bus, wishbone2csr
from misoc.integration.config import Config

@@ -23,6 +23,7 @@ class SoCCore(Module):
"timer0": 4, # provided by default (optional)
"buttons": 5, # user
"leds": 6, # user
"tmpu": 31, # provided
}
interrupt_map = {
"uart": 0,
@@ -79,8 +80,9 @@ def __init__(self, platform, clk_freq,
self.submodules.cpu = mor1kx.MOR1KX(platform, self.cpu_reset_address)
else:
raise ValueError("Unsupported CPU type: {}".format(cpu_type))
self.submodules.tmpu = tmpu.TMPU(self.cpu.dbus)
self.add_wb_master(self.cpu.ibus)
self.add_wb_master(self.cpu.dbus)
self.add_wb_master(self.tmpu.output_bus)

if integrated_rom_size:
self.submodules.rom = wishbone.SRAM(integrated_rom_size, read_only=True)
5 changes: 5 additions & 0 deletions misoc/interconnect/csr_bus.py
Original file line number Diff line number Diff line change
@@ -20,6 +20,11 @@ def __init__(self, data_width=8, address_width=14):
Record.__init__(self, set_layout_parameters(_layout,
data_width=data_width, address_width=address_width))

@classmethod
def like(self, other):
return Interface(len(other.dat_w),
len(other.adr))

def write(self, adr, dat):
yield self.adr.eq(adr)
yield self.dat_w.eq(dat)
4 changes: 4 additions & 0 deletions misoc/interconnect/wishbone.py
Original file line number Diff line number Diff line change
@@ -33,6 +33,10 @@ def __init__(self, data_width=32):
data_width=data_width,
sel_width=data_width//8))

@staticmethod
def like(other):
return Interface(len(other.dat_w))

def _do_transaction(self):
yield self.cyc.eq(1)
yield self.stb.eq(1)