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tmpu: fix page_bits computation
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sbourdeauducq committed Sep 24, 2016
1 parent f6e4882 commit 26ecb6a
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions misoc/cores/tmpu.py
Original file line number Diff line number Diff line change
@@ -29,9 +29,9 @@ def __init__(self, input_bus, page_size=4096):
self.output_bus = wishbone.Interface.like(input_bus)

word_bits = log2_int(len(input_bus.dat_w)//8)
page_bits = log2_int(page_size//8) - word_bits
page_bits = log2_int(page_size) - word_bits

self.page_size = CSRConstant(2**(word_bits+page_bits))
self.page_size = CSRConstant(page_size)
self.enable_null = CSRStorage()
self.enable_prog = CSRStorage()
self.prog_address = CSRStorage(len(input_bus.adr),

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