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automatically generate CSR and interrupt maps
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sbourdeauducq committed Sep 24, 2016
1 parent 26ecb6a commit 6af3e1b
Showing 7 changed files with 38 additions and 82 deletions.
46 changes: 24 additions & 22 deletions misoc/integration/soc_core.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,3 @@
from operator import itemgetter

from migen import *

from misoc.cores import lm32, mor1kx, tmpu, identifier, timer, uart
@@ -15,20 +13,6 @@ def mem_decoder(address, start=26, end=29):


class SoCCore(Module):
csr_map = {
"crg": 0, # user
"uart_phy": 1, # provided by default (optional)
"uart": 2, # provided by default (optional)
"identifier_mem": 3, # provided by default (optional)
"timer0": 4, # provided by default (optional)
"buttons": 5, # user
"leds": 6, # user
"tmpu": 31, # provided
}
interrupt_map = {
"uart": 0,
"timer0": 1,
}
mem_map = {
"rom": 0x00000000, # (default shadow @0x80000000)
"sram": 0x10000000, # (default shadow @0x90000000)
@@ -74,6 +58,15 @@ def __init__(self, platform, clk_freq,

self.config = Config()

self.csr_devices = [
"uart_phy",
"uart",
"identifier_mem",
"timer0",
"tmpu"
]
self.interrupt_devices = []

if cpu_type == "lm32":
self.submodules.cpu = lm32.LM32(platform, self.cpu_reset_address)
elif cpu_type == "or1k":
@@ -104,13 +97,15 @@ def __init__(self, platform, clk_freq,
if with_uart:
self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate)
self.submodules.uart = uart.UART(self.uart_phy)
self.interrupt_devices.append("uart")

if ident:
self.submodules.identifier = identifier.Identifier(ident)
self.config["CLOCK_FREQUENCY"] = int(clk_freq)

if with_timer:
self.submodules.timer0 = timer.Timer()
self.interrupt_devices.append("timer0")

def initialize_rom(self, data):
self.rom.mem.init = data
@@ -160,11 +155,19 @@ def get_csr_regions(self):

def get_constants(self):
r = []
for name, interrupt in sorted(self.interrupt_map.items(), key=itemgetter(1)):
r.append((name.upper() + "_INTERRUPT", interrupt))
for nr, name in enumerate(self.interrupt_devices):
r.append((name.upper() + "_INTERRUPT", nr))
r += self._constants
return r

def get_csr_dev_address(self, name, memory):
if memory is not None:
name = name + "_" + memory.name_override
try:
return self.csr_devices.index(name)
except ValueError:
return None

def do_finalize(self):
registered_mems = {regions[0] for regions in self._memory_regions}
for mem in "rom", "sram":
@@ -177,7 +180,7 @@ def do_finalize(self):

# CSR
self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
self.get_csr_dev_address,
data_width=self.csr_data_width, address_width=self.csr_address_width)
self.submodules.csrcon = csr_bus.Interconnect(
self.wishbone2csr.csr, self.csrbankarray.get_buses())
@@ -189,9 +192,8 @@ def do_finalize(self):
self._constants.append(((name + "_" + constant.name).upper(), constant.value.value))

# Interrupts
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
if hasattr(self, k):
self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
for nr, name in enumerate(self.interrupt_devices):
self.comb += self.cpu.interrupt[nr].eq(getattr(self, name).ev.irq)

def build(self, *args, **kwargs):
self.platform.build(self, *args, **kwargs)
7 changes: 1 addition & 6 deletions misoc/integration/soc_sdram.py
Original file line number Diff line number Diff line change
@@ -11,15 +11,10 @@


class SoCSDRAM(SoCCore):
csr_map = {
"dfii": 7,
"l2_cache": 8
}
csr_map.update(SoCCore.csr_map)

def __init__(self, platform, clk_freq, l2_size=8192, **kwargs):
SoCCore.__init__(self, platform, clk_freq,
integrated_main_ram_size=0, **kwargs)
self.csr_devices += ["dfii", "l2_cache"]

if l2_size:
self.config["L2_SIZE"] = l2_size
21 changes: 4 additions & 17 deletions misoc/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -76,17 +76,12 @@ def __init__(self, platform):
class BaseSoC(SoCSDRAM):
default_platform = "kc705"

csr_map = {
"spiflash": 9,
"ddrphy": 10,
}
csr_map.update(SoCSDRAM.csr_map)

def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs):
platform = kc705.Platform(toolchain=toolchain)
SoCSDRAM.__init__(self, platform,
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
**kwargs)
self.csr_devices += ["spiflash", "ddrphy"]

self.submodules.crg = _CRG(platform)

@@ -109,17 +104,6 @@ def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs


class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 11,
"ethmac": 12,
}
csr_map.update(BaseSoC.csr_map)

interrupt_map = {
"ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)

mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
@@ -128,6 +112,9 @@ class MiniSoC(BaseSoC):
def __init__(self, *args, **kwargs):
BaseSoC.__init__(self, *args, **kwargs)

self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")

self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
self.platform.request("eth"), clk_freq=self.clk_freq)
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
21 changes: 5 additions & 16 deletions misoc/targets/mlabs_video.py
Original file line number Diff line number Diff line change
@@ -117,17 +117,6 @@ def __init__(self, platform_name="mixxeo", **kwargs):


class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 16,
"ethmac": 17,
}
csr_map.update(BaseSoC.csr_map)

interrupt_map = {
"ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)

mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
@@ -139,16 +128,20 @@ def __init__(self, *args, **kwargs):
platform = self.platform
if platform.name == "mixxeo":
self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
self.csr_devices.append("leds")
if platform.name == "m1":
self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0),
platform.request("user_btn", 2)))
self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2)))
self.csr_devices += ["buttons", "leds"]

self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
platform.request("eth"))
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")


def get_vga_dvi(platform):
@@ -177,17 +170,13 @@ def add_vga_tig(platform, fb):


class FramebufferSoC(MiniSoC):
csr_map = {
"fb": 18,
}
csr_map.update(MiniSoC.csr_map)

def __init__(self, *args, **kwargs):
MiniSoC.__init__(self, *args, **kwargs)
pads_vga, pads_dvi = get_vga_dvi(platform)
self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi,
self.get_native_sdram_if())
add_vga_tig(platform, self.fb)
self.csr_devices.append("fb")


def main():
6 changes: 1 addition & 5 deletions misoc/targets/papilio_pro.py
Original file line number Diff line number Diff line change
@@ -66,11 +66,6 @@ def __init__(self, platform, clk_freq):


class BaseSoC(SoCSDRAM):
csr_map = {
"spiflash": 16,
}
csr_map.update(SoCSDRAM.csr_map)

def __init__(self, **kwargs):
platform = papilio_pro.Platform()
clk_freq = 80*1000000
@@ -90,6 +85,7 @@ def __init__(self, **kwargs):
dummy=4, div=6)
self.flash_boot_address = 0x70000
self.register_rom(self.spiflash.bus)
self.csr_devices.append("spiflash")


def main():
6 changes: 1 addition & 5 deletions misoc/targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -95,11 +95,6 @@ def __init__(self, platform, clk_freq):


class BaseSoC(SoCSDRAM):
csr_map = {
"spiflash": 9,
}
csr_map.update(SoCSDRAM.csr_map)

def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
platform = pipistrello.Platform()
SoCSDRAM.__init__(self, platform, clk_freq,
@@ -128,6 +123,7 @@ def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
self.flash_boot_address = 0x180000
self.register_rom(self.spiflash.bus, 0x1000000)
self.csr_devices.append("spiflash")


soc_pipistrello_args = soc_sdram_args
13 changes: 2 additions & 11 deletions misoc/targets/simple.py
Original file line number Diff line number Diff line change
@@ -23,17 +23,6 @@ def __init__(self, platform, **kwargs):


class MiniSoC(BaseSoC):
csr_map = {
"ethphy": 20,
"ethmac": 21
}
csr_map.update(BaseSoC.csr_map)

interrupt_map = {
"ethmac": 2,
}
interrupt_map.update(BaseSoC.interrupt_map)

mem_map = {
"ethmac": 0x30000000, # (shadow @0xb0000000)
}
@@ -49,6 +38,8 @@ def __init__(self, platform, **kwargs):
with_preamble_crc=False)
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
self.csr_devices += ["ethphy", "ethmac"]
self.interrupt_devices.append("ethmac")


def main():

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