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sbourdeauducqsbourdeauducq
committedSep 24, 2016
automatically generate CSR and interrupt maps
1 parent 26ecb6a commit 6af3e1b

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7 files changed

+38
-82
lines changed

7 files changed

+38
-82
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Diff for: ‎misoc/integration/soc_core.py

+24-22
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
from operator import itemgetter
2-
31
from migen import *
42

53
from misoc.cores import lm32, mor1kx, tmpu, identifier, timer, uart
@@ -15,20 +13,6 @@ def mem_decoder(address, start=26, end=29):
1513

1614

1715
class SoCCore(Module):
18-
csr_map = {
19-
"crg": 0, # user
20-
"uart_phy": 1, # provided by default (optional)
21-
"uart": 2, # provided by default (optional)
22-
"identifier_mem": 3, # provided by default (optional)
23-
"timer0": 4, # provided by default (optional)
24-
"buttons": 5, # user
25-
"leds": 6, # user
26-
"tmpu": 31, # provided
27-
}
28-
interrupt_map = {
29-
"uart": 0,
30-
"timer0": 1,
31-
}
3216
mem_map = {
3317
"rom": 0x00000000, # (default shadow @0x80000000)
3418
"sram": 0x10000000, # (default shadow @0x90000000)
@@ -74,6 +58,15 @@ def __init__(self, platform, clk_freq,
7458

7559
self.config = Config()
7660

61+
self.csr_devices = [
62+
"uart_phy",
63+
"uart",
64+
"identifier_mem",
65+
"timer0",
66+
"tmpu"
67+
]
68+
self.interrupt_devices = []
69+
7770
if cpu_type == "lm32":
7871
self.submodules.cpu = lm32.LM32(platform, self.cpu_reset_address)
7972
elif cpu_type == "or1k":
@@ -104,13 +97,15 @@ def __init__(self, platform, clk_freq,
10497
if with_uart:
10598
self.submodules.uart_phy = uart.RS232PHY(platform.request("serial"), clk_freq, uart_baudrate)
10699
self.submodules.uart = uart.UART(self.uart_phy)
100+
self.interrupt_devices.append("uart")
107101

108102
if ident:
109103
self.submodules.identifier = identifier.Identifier(ident)
110104
self.config["CLOCK_FREQUENCY"] = int(clk_freq)
111105

112106
if with_timer:
113107
self.submodules.timer0 = timer.Timer()
108+
self.interrupt_devices.append("timer0")
114109

115110
def initialize_rom(self, data):
116111
self.rom.mem.init = data
@@ -160,11 +155,19 @@ def get_csr_regions(self):
160155

161156
def get_constants(self):
162157
r = []
163-
for name, interrupt in sorted(self.interrupt_map.items(), key=itemgetter(1)):
164-
r.append((name.upper() + "_INTERRUPT", interrupt))
158+
for nr, name in enumerate(self.interrupt_devices):
159+
r.append((name.upper() + "_INTERRUPT", nr))
165160
r += self._constants
166161
return r
167162

163+
def get_csr_dev_address(self, name, memory):
164+
if memory is not None:
165+
name = name + "_" + memory.name_override
166+
try:
167+
return self.csr_devices.index(name)
168+
except ValueError:
169+
return None
170+
168171
def do_finalize(self):
169172
registered_mems = {regions[0] for regions in self._memory_regions}
170173
for mem in "rom", "sram":
@@ -177,7 +180,7 @@ def do_finalize(self):
177180

178181
# CSR
179182
self.submodules.csrbankarray = csr_bus.CSRBankArray(self,
180-
lambda name, memory: self.csr_map[name if memory is None else name + "_" + memory.name_override],
183+
self.get_csr_dev_address,
181184
data_width=self.csr_data_width, address_width=self.csr_address_width)
182185
self.submodules.csrcon = csr_bus.Interconnect(
183186
self.wishbone2csr.csr, self.csrbankarray.get_buses())
@@ -189,9 +192,8 @@ def do_finalize(self):
189192
self._constants.append(((name + "_" + constant.name).upper(), constant.value.value))
190193

191194
# Interrupts
192-
for k, v in sorted(self.interrupt_map.items(), key=itemgetter(1)):
193-
if hasattr(self, k):
194-
self.comb += self.cpu.interrupt[v].eq(getattr(self, k).ev.irq)
195+
for nr, name in enumerate(self.interrupt_devices):
196+
self.comb += self.cpu.interrupt[nr].eq(getattr(self, name).ev.irq)
195197

196198
def build(self, *args, **kwargs):
197199
self.platform.build(self, *args, **kwargs)

Diff for: ‎misoc/integration/soc_sdram.py

+1-6
Original file line numberDiff line numberDiff line change
@@ -11,15 +11,10 @@
1111

1212

1313
class SoCSDRAM(SoCCore):
14-
csr_map = {
15-
"dfii": 7,
16-
"l2_cache": 8
17-
}
18-
csr_map.update(SoCCore.csr_map)
19-
2014
def __init__(self, platform, clk_freq, l2_size=8192, **kwargs):
2115
SoCCore.__init__(self, platform, clk_freq,
2216
integrated_main_ram_size=0, **kwargs)
17+
self.csr_devices += ["dfii", "l2_cache"]
2318

2419
if l2_size:
2520
self.config["L2_SIZE"] = l2_size

Diff for: ‎misoc/targets/kc705.py

+4-17
Original file line numberDiff line numberDiff line change
@@ -76,17 +76,12 @@ def __init__(self, platform):
7676
class BaseSoC(SoCSDRAM):
7777
default_platform = "kc705"
7878

79-
csr_map = {
80-
"spiflash": 9,
81-
"ddrphy": 10,
82-
}
83-
csr_map.update(SoCSDRAM.csr_map)
84-
8579
def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs):
8680
platform = kc705.Platform(toolchain=toolchain)
8781
SoCSDRAM.__init__(self, platform,
8882
clk_freq=125*1000000, cpu_reset_address=0xaf0000,
8983
**kwargs)
84+
self.csr_devices += ["spiflash", "ddrphy"]
9085

9186
self.submodules.crg = _CRG(platform)
9287

@@ -109,17 +104,6 @@ def __init__(self, toolchain="vivado", sdram_controller_type="minicon", **kwargs
109104

110105

111106
class MiniSoC(BaseSoC):
112-
csr_map = {
113-
"ethphy": 11,
114-
"ethmac": 12,
115-
}
116-
csr_map.update(BaseSoC.csr_map)
117-
118-
interrupt_map = {
119-
"ethmac": 2,
120-
}
121-
interrupt_map.update(BaseSoC.interrupt_map)
122-
123107
mem_map = {
124108
"ethmac": 0x30000000, # (shadow @0xb0000000)
125109
}
@@ -128,6 +112,9 @@ class MiniSoC(BaseSoC):
128112
def __init__(self, *args, **kwargs):
129113
BaseSoC.__init__(self, *args, **kwargs)
130114

115+
self.csr_devices += ["ethphy", "ethmac"]
116+
self.interrupt_devices.append("ethmac")
117+
131118
self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"),
132119
self.platform.request("eth"), clk_freq=self.clk_freq)
133120
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")

Diff for: ‎misoc/targets/mlabs_video.py

+5-16
Original file line numberDiff line numberDiff line change
@@ -117,17 +117,6 @@ def __init__(self, platform_name="mixxeo", **kwargs):
117117

118118

119119
class MiniSoC(BaseSoC):
120-
csr_map = {
121-
"ethphy": 16,
122-
"ethmac": 17,
123-
}
124-
csr_map.update(BaseSoC.csr_map)
125-
126-
interrupt_map = {
127-
"ethmac": 2,
128-
}
129-
interrupt_map.update(BaseSoC.interrupt_map)
130-
131120
mem_map = {
132121
"ethmac": 0x30000000, # (shadow @0xb0000000)
133122
}
@@ -139,16 +128,20 @@ def __init__(self, *args, **kwargs):
139128
platform = self.platform
140129
if platform.name == "mixxeo":
141130
self.submodules.leds = gpio.GPIOOut(platform.request("user_led"))
131+
self.csr_devices.append("leds")
142132
if platform.name == "m1":
143133
self.submodules.buttons = gpio.GPIOIn(Cat(platform.request("user_btn", 0),
144134
platform.request("user_btn", 2)))
145135
self.submodules.leds = gpio.GPIOOut(Cat(platform.request("user_led", i) for i in range(2)))
136+
self.csr_devices += ["buttons", "leds"]
146137

147138
self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"),
148139
platform.request("eth"))
149140
self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone")
150141
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
151142
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
143+
self.csr_devices += ["ethphy", "ethmac"]
144+
self.interrupt_devices.append("ethmac")
152145

153146

154147
def get_vga_dvi(platform):
@@ -177,17 +170,13 @@ def add_vga_tig(platform, fb):
177170

178171

179172
class FramebufferSoC(MiniSoC):
180-
csr_map = {
181-
"fb": 18,
182-
}
183-
csr_map.update(MiniSoC.csr_map)
184-
185173
def __init__(self, *args, **kwargs):
186174
MiniSoC.__init__(self, *args, **kwargs)
187175
pads_vga, pads_dvi = get_vga_dvi(platform)
188176
self.submodules.fb = framebuffer.Framebuffer(pads_vga, pads_dvi,
189177
self.get_native_sdram_if())
190178
add_vga_tig(platform, self.fb)
179+
self.csr_devices.append("fb")
191180

192181

193182
def main():

Diff for: ‎misoc/targets/papilio_pro.py

+1-5
Original file line numberDiff line numberDiff line change
@@ -66,11 +66,6 @@ def __init__(self, platform, clk_freq):
6666

6767

6868
class BaseSoC(SoCSDRAM):
69-
csr_map = {
70-
"spiflash": 16,
71-
}
72-
csr_map.update(SoCSDRAM.csr_map)
73-
7469
def __init__(self, **kwargs):
7570
platform = papilio_pro.Platform()
7671
clk_freq = 80*1000000
@@ -90,6 +85,7 @@ def __init__(self, **kwargs):
9085
dummy=4, div=6)
9186
self.flash_boot_address = 0x70000
9287
self.register_rom(self.spiflash.bus)
88+
self.csr_devices.append("spiflash")
9389

9490

9591
def main():

Diff for: ‎misoc/targets/pipistrello.py

+1-5
Original file line numberDiff line numberDiff line change
@@ -95,11 +95,6 @@ def __init__(self, platform, clk_freq):
9595

9696

9797
class BaseSoC(SoCSDRAM):
98-
csr_map = {
99-
"spiflash": 9,
100-
}
101-
csr_map.update(SoCSDRAM.csr_map)
102-
10398
def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
10499
platform = pipistrello.Platform()
105100
SoCSDRAM.__init__(self, platform, clk_freq,
@@ -128,6 +123,7 @@ def __init__(self, clk_freq=(83 + Fraction(1, 3))*1000*1000, **kwargs):
128123
self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
129124
self.flash_boot_address = 0x180000
130125
self.register_rom(self.spiflash.bus, 0x1000000)
126+
self.csr_devices.append("spiflash")
131127

132128

133129
soc_pipistrello_args = soc_sdram_args

Diff for: ‎misoc/targets/simple.py

+2-11
Original file line numberDiff line numberDiff line change
@@ -23,17 +23,6 @@ def __init__(self, platform, **kwargs):
2323

2424

2525
class MiniSoC(BaseSoC):
26-
csr_map = {
27-
"ethphy": 20,
28-
"ethmac": 21
29-
}
30-
csr_map.update(BaseSoC.csr_map)
31-
32-
interrupt_map = {
33-
"ethmac": 2,
34-
}
35-
interrupt_map.update(BaseSoC.interrupt_map)
36-
3726
mem_map = {
3827
"ethmac": 0x30000000, # (shadow @0xb0000000)
3928
}
@@ -49,6 +38,8 @@ def __init__(self, platform, **kwargs):
4938
with_preamble_crc=False)
5039
self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus)
5140
self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000)
41+
self.csr_devices += ["ethphy", "ethmac"]
42+
self.interrupt_devices.append("ethmac")
5243

5344

5445
def main():

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