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gateware: use new misoc CSR mapping API
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sbourdeauducq committed Sep 24, 2016
1 parent 956f649 commit 8280e72
Showing 3 changed files with 8 additions and 24 deletions.
4 changes: 1 addition & 3 deletions artiq/gateware/soc.py
Original file line number Diff line number Diff line change
@@ -26,6 +26,7 @@ def __init__(self):

self.submodules.kernel_cpu = amp.KernelCPU(self.platform)
self.add_cpulevel_sdram_if(self.kernel_cpu.wb_sdram)
self.csr_devices.append("kernel_cpu")

self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
@@ -39,9 +40,6 @@ def __init__(self):
self.register_kernel_cpu_csrdevice("timer_kernel")

def register_kernel_cpu_csrdevice(self, name):
# make sure the device is not getting connected to the comms-CPU already
assert self.csr_map[name] is None

csrs = getattr(self, name).get_csrs()
bank = wishbone.CSRBank(csrs)
self.submodules += bank
16 changes: 4 additions & 12 deletions artiq/gateware/targets/kc705.py
Original file line number Diff line number Diff line change
@@ -101,18 +101,6 @@ def __init__(self, platform, rtio_internal_clk):


class _NIST_Ions(MiniSoC, AMPSoC):
csr_map = {
# mapped on Wishbone instead
"timer_kernel": None,
"rtio": None,
"i2c": None,

"rtio_crg": 13,
"kernel_cpu": 14,
"rtio_moninj": 15,
"rtio_analyzer": 16
}
csr_map.update(MiniSoC.csr_map)
mem_map = {
"timer_kernel": 0x10000000, # (shadow @0x90000000)
"rtio": 0x20000000, # (shadow @0xa0000000)
@@ -140,6 +128,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
self.submodules.leds = gpio.GPIOOut(Cat(
self.platform.request("user_led", 0),
self.platform.request("user_led", 1)))
self.csr_devices.append("leds")

self.platform.add_extension(_sma33_io)
self.platform.add_extension(_ams101_dac)
@@ -151,10 +140,12 @@ def __init__(self, cpu_type="or1k", **kwargs):

def add_rtio(self, rtio_channels):
self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
self.csr_devices.append("rtio_crg")
self.submodules.rtio = rtio.RTIO(rtio_channels)
self.register_kernel_cpu_csrdevice("rtio")
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")

self.specials += [
Keep(self.rtio.cd_rsys.clk),
@@ -175,6 +166,7 @@ def add_rtio(self, rtio_channels):

self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")


class NIST_QC1(_NIST_Ions):
12 changes: 3 additions & 9 deletions artiq/gateware/targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -125,15 +125,6 @@ def __init__(self, platform, clk_freq):


class NIST_QC1(BaseSoC, AMPSoC):
csr_map = {
"timer_kernel": None, # mapped on Wishbone instead
"rtio": None, # mapped on Wishbone instead
"rtio_crg": 10,
"kernel_cpu": 11,
"rtio_moninj": 12,
"rtio_analyzer": 13
}
csr_map.update(BaseSoC.csr_map)
mem_map = {
"timer_kernel": 0x10000000, # (shadow @0x90000000)
"rtio": 0x20000000, # (shadow @0xa0000000)
@@ -168,6 +159,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
]

self.submodules.rtio_crg = _RTIOCRG(platform, self.clk_freq)
self.csr_devices.append("rtio_crg")

# RTIO channels
rtio_channels = []
@@ -235,8 +227,10 @@ def __init__(self, cpu_type="or1k", **kwargs):
self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
self.config["DDS_RTIO_CLK_RATIO"] = 8 >> self.rtio.fine_ts_width
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj")
self.submodules.rtio_analyzer = rtio.Analyzer(
self.rtio, self.get_native_sdram_if())
self.csr_devices.append("rtio_analyzer")


def main():

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