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pipistrello: shrink a few more fifos
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jordens committed Sep 21, 2016
1 parent 6d715d0 commit 122d48d
Showing 1 changed file with 2 additions and 2 deletions.
4 changes: 2 additions & 2 deletions artiq/gateware/targets/pipistrello.py
Original file line number Diff line number Diff line change
@@ -176,7 +176,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
self.rtio_crg.rtiox4_stb)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256,
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
ofifo_depth=4))

# the last TTL is used for ClockGen
@@ -223,7 +223,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
phy = dds.AD9858(dds_pins, 8)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy,
ofifo_depth=256,
ofifo_depth=128,
ififo_depth=4))

self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)

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