pipistrello: shrink a few more fifos

jordens · jordens · commit 122d48d2d530 · 2016-09-21T02:45:52.000+02:00
diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
@@ -176,7 +176,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
             phy = ttl_serdes_spartan6.Inout_4X(platform.request("pmt", i),
                                                self.rtio_crg.rtiox4_stb)
             self.submodules += phy
-            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=256,
+            rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=128,
                                                        ofifo_depth=4))
 
         # the last TTL is used for ClockGen
@@ -223,7 +223,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
         phy = dds.AD9858(dds_pins, 8)
         self.submodules += phy
         rtio_channels.append(rtio.Channel.from_phy(phy,
-                                                   ofifo_depth=256,
+                                                   ofifo_depth=128,
                                                    ififo_depth=4))
 
         self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
