Are you sure the old QC2 corresponds to the clock backplane? David has this clock backplane (right?) and he had to make a lot of changes to the QC2 pinout to get it to work, e.g.

 fmc_adapter_io = [
-    ("ttl", 0, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
+    ("ttl", 0, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
     ("ttl", 1, Pins("LPC:LA02_P"), IOStandard("LVTTL")),
-    ("ttl", 2, Pins("LPC:LA00_CC_N"), IOStandard("LVTTL")),
+    ("ttl", 2, Pins("LPC:LA00_CC_P"), IOStandard("LVTTL")),
     ("ttl", 3, Pins("LPC:LA02_N"), IOStandard("LVTTL")),
-    ("ttl", 4, Pins("LPC:LA01_CC_P"), IOStandard("LVTTL")),
-    ("ttl", 5, Pins("LPC:LA01_CC_N"), IOStandard("LVTTL")),
-    ("ttl", 6, Pins("LPC:LA06_P"), IOStandard("LVTTL")),
-    ("ttl", 7, Pins("LPC:LA06_N"), IOStandard("LVTTL")),
-    ("ttl", 8, Pins("LPC:LA05_P"), IOStandard("LVTTL")),
+    ("ttl", 4, Pins("LPC:LA01_CC_N"), IOStandard("LVTTL")),
+    ("ttl", 5, Pins("LPC:LA06_P"), IOStandard("LVTTL")),
+    ("ttl", 6, Pins("LPC:LA06_N"), IOStandard("LVTTL")),
+    ("ttl", 7, Pins("LPC:LA27_P"), IOStandard("LVTTL")),
+    ("ttl", 8, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
     ("ttl", 9, Pins("LPC:LA05_N"), IOStandard("LVTTL")),
-    ("ttl", 10, Pins("LPC:LA10_P"), IOStandard("LVTTL")),
+    ("ttl", 10, Pins("LPC:LA05_P"), IOStandard("LVTTL")),
     ("ttl", 11, Pins("LPC:LA09_P"), IOStandard("LVTTL")),
-    ("ttl", 12, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
-    ("ttl", 13, Pins("LPC:LA09_N"), IOStandard("LVTTL")),
-    ("ttl", 14, Pins("LPC:LA13_P"), IOStandard("LVTTL")),
-    ("ttl", 15, Pins("LPC:LA14_P"), IOStandard("LVTTL")),
+    ("ttl", 12, Pins("LPC:LA09_N"), IOStandard("LVTTL")),
+    ("ttl", 13, Pins("LPC:LA13_P"), IOStandard("LVTTL")),
+    ("ttl", 14, Pins("LPC:LA14_P"), IOStandard("LVTTL")),
+    ("ttl", 15, Pins("LPC:LA10_N"), IOStandard("LVTTL")),
+    
+    ("pmt", 0, Pins("LPC:CLK0_M2C_P"), IOStandard("LVTTL")),
+    ("pmt", 1, Pins("LPC:CLK0_M2C_N"), IOStandard("LVTTL")),

     ("dds", 0,
         Subsignal("a", Pins("LPC:LA22_N LPC:LA21_P LPC:LA22_P LPC:LA19_N "

I'm pretty sure that old QC2 really is the same as the clock hardware, but that perhaps not all of the TTL lines were ever tested. Additionally, some of my pinout changes are due to the fact that the numbering of the TTL lines was not the same as on the clock breakout panel. In any case, I'm pretty sure that I'm the only one using the old QC2 configuration, so as long as you create a clock configuration based on the old QC2 with my pinout changes I think everyone will be happy.

I based the pinouts for the clock backplane on the labeling scheme used in Till's schematic for the clock backplane. We intentionally designed the new QC2 backplane to have an identical FMC pinout as the clock backplane, with only minor changes of adding one DDS SEL line (eliminating the LA_32 pair), renaming the SPI lines to TTL lines, and connecting the JTAG TDI to TDO. However, it seems that somehow the lines are renamed in the clock backplane. It seems to me that @dleibrandt is right, as long as you use the pinouts he specifies for the clock backplane everyone will be happy. In my patch I simply copied what was already in the NIST_QC2, assuming these edits had already been incorporated.

TODO:

• conda packaging
• buildbot update
• documentation for QC2
• update install instructions to mention CLOCK
• support for the flashing script
• rename _NIST_QCx as this is no longer an appropriate name for this class (I will fix this)
• -H option in kc705.py (I will fix this)

@dhslichter @dleibrandt I have integrated your various modifications. Can you check that the current gateware matches the hardware?

Items 1-5 above still need to be done.

1-2 are done.

5 is unnecessary, -m clock just works. 3-4 still needed.

Ping

occupied with other projects last week, will complete testing and submit doc patch hopefully this week.