kasli: add target

jordens · jordens · commit c36813ec8c50 · 2017-10-11T13:03:09.000+02:00
diff --git a/misoc/targets/kasli.py b/misoc/targets/kasli.py
@@ -0,0 +1,123 @@
+#!/usr/bin/env python3
+
+import argparse
+
+from migen import *
+from migen.genlib.resetsync import AsyncResetSynchronizer
+from migen.build.platforms.sinara import kasli
+
+from misoc.cores.sdram_settings import MT41K256M16
+from misoc.cores.sdram_phy import a7ddrphy
+from misoc.cores import spi_flash
+from misoc.integration.soc_sdram import *
+from misoc.integration.builder import *
+
+
+class _CRG(Module):
+    def __init__(self, platform):
+        self.clock_domains.cd_sys = ClockDomain()
+        self.clock_domains.cd_sys4x = ClockDomain(reset_less=True)
+        self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
+        self.clock_domains.cd_clk200 = ClockDomain()
+
+        clk50 = platform.request("clk50")
+
+        pll_locked = Signal()
+        pll_fb = Signal()
+        pll_sys = Signal()
+        pll_sys4x = Signal()
+        pll_sys4x_dqs = Signal()
+        pll_clk200 = Signal()
+        self.specials += [
+            Instance("PLLE2_BASE",
+                     p_STARTUP_WAIT="FALSE", o_LOCKED=pll_locked,
+
+                     # VCO @ 1GHz
+                     p_REF_JITTER1=0.01, p_CLKIN1_PERIOD=20.0,
+                     p_CLKFBOUT_MULT=20, p_DIVCLK_DIVIDE=1,
+                     i_CLKIN1=clk50, i_CLKFBIN=pll_fb, o_CLKFBOUT=pll_fb,
+
+                     # 125MHz
+                     p_CLKOUT0_DIVIDE=8, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=pll_sys,
+
+                     # 500MHz
+                     p_CLKOUT1_DIVIDE=2, p_CLKOUT1_PHASE=0.0, o_CLKOUT1=pll_sys4x,
+
+                     # 200MHz
+                     p_CLKOUT2_DIVIDE=5, p_CLKOUT2_PHASE=0.0, o_CLKOUT2=pll_clk200,
+
+                     p_CLKOUT3_DIVIDE=2, p_CLKOUT3_PHASE=90.0, o_CLKOUT3=pll_sys4x_dqs,
+
+                     p_CLKOUT4_DIVIDE=4, p_CLKOUT4_PHASE=0.0, #o_CLKOUT4=
+            ),
+            Instance("BUFG", i_I=pll_sys, o_O=self.cd_sys.clk),
+            Instance("BUFG", i_I=pll_sys4x, o_O=self.cd_sys4x.clk),
+            Instance("BUFG", i_I=pll_sys4x_dqs, o_O=self.cd_sys4x_dqs.clk),
+            Instance("BUFG", i_I=pll_clk200, o_O=self.cd_clk200.clk),
+            AsyncResetSynchronizer(self.cd_sys, ~pll_locked),
+            AsyncResetSynchronizer(self.cd_clk200, ~pll_locked),
+        ]
+
+        reset_counter = Signal(4, reset=15)
+        ic_reset = Signal(reset=1)
+        self.sync.clk200 += \
+            If(reset_counter != 0,
+                reset_counter.eq(reset_counter - 1)
+            ).Else(
+                ic_reset.eq(0)
+            )
+        self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
+
+
+class BaseSoC(SoCSDRAM):
+    def __init__(self, sdram_controller_type="minicon", **kwargs):
+        platform = kasli.Platform()
+        SoCSDRAM.__init__(self, platform,
+                          clk_freq=125*1000000, cpu_reset_address=0xaf0000,
+                          **kwargs)
+
+        self.submodules.crg = _CRG(platform)
+
+        self.submodules.ddrphy = a7ddrphy.A7DDRPHY(platform.request("ddram"))
+        sdram_module = MT41K256M16(self.clk_freq, "1:4")
+        self.register_sdram(self.ddrphy, sdram_controller_type,
+                            sdram_module.geom_settings, sdram_module.timing_settings)
+        self.csr_devices.append("ddrphy")
+
+        if not self.integrated_rom_size:
+            spiflash_pads = platform.request("spiflash")
+            spiflash_pads.clk = Signal()
+            self.specials += Instance("STARTUPE2",
+                                      i_CLK=0, i_GSR=0, i_GTS=0, i_KEYCLEARB=0, i_PACK=0,
+                                      i_USRCCLKO=spiflash_pads.clk, i_USRCCLKTS=0, i_USRDONEO=1, i_USRDONETS=1)
+            self.submodules.spiflash = spi_flash.SpiFlash(spiflash_pads, dummy=11, div=2)
+            self.config["SPIFLASH_PAGE_SIZE"] = 256
+            self.config["SPIFLASH_SECTOR_SIZE"] = 0x10000
+            self.flash_boot_address = 0xb00000
+            self.register_rom(self.spiflash.bus, 16*1024*1024)
+            self.csr_devices.append("spiflash")
+
+
+def soc_kasli_args(parser):
+    soc_sdram_args(parser)
+
+
+def soc_kasli_argdict(args):
+    r = soc_sdram_argdict(args)
+    return r
+
+
+def main():
+    parser = argparse.ArgumentParser(description="MiSoC port to Kasli")
+    builder_args(parser)
+    soc_kasli_args(parser)
+    args = parser.parse_args()
+
+    cls = BaseSoC
+    soc = cls(**soc_kasli_argdict(args))
+    builder = Builder(soc, **builder_argdict(args))
+    builder.build()
+
+
+if __name__ == "__main__":
+    main()
