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144 | 144 | Subsignal("rx_n", Pins("B12")), # rtm_fpga_lvds2_n
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145 | 145 | IOStandard("LVDS")
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146 | 146 | ),
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| 147 | + |
| 148 | + # AD9154 DACs |
| 149 | + ("dac_refclk", 0, |
| 150 | + Subsignal("p", Pins("V6")), |
| 151 | + Subsignal("n", Pins("V5")), |
| 152 | + ), |
| 153 | + ("dac_refclk", 1, |
| 154 | + Subsignal("p", Pins("P6")), |
| 155 | + Subsignal("n", Pins("P5")), |
| 156 | + ), |
| 157 | + ("dac_sysref", 0, |
| 158 | + Subsignal("p", Pins("B10")), |
| 159 | + Subsignal("n", Pins("A10")), |
| 160 | + IOStandard("LVDS") |
| 161 | + ), |
| 162 | + ("dac_sync", 0, |
| 163 | + Subsignal("p", Pins("L8")), |
| 164 | + Subsignal("n", Pins("K8")), |
| 165 | + IOStandard("LVDS") |
| 166 | + ), |
| 167 | + ("dac_sync", 1, |
| 168 | + Subsignal("p", Pins("J9")), |
| 169 | + Subsignal("n", Pins("H9")), |
| 170 | + IOStandard("LVDS") |
| 171 | + ), |
| 172 | + ("dac_jesd", 0, |
| 173 | + Subsignal("txp", Pins("R4 U4 W4 AA4 AC4 AE4 AG4 AH6")), |
| 174 | + Subsignal("txn", Pins("R3 U3 W3 AA3 AC3 AE3 AG3 AH5")) |
| 175 | + ), |
| 176 | + ("dac_jesd", 1, |
| 177 | + Subsignal("txp", Pins("B6 C4 D6 F6 G4 J4 L4 N4")), |
| 178 | + Subsignal("txn", Pins("B5 C3 D5 F5 G3 J3 L3 N3")) |
| 179 | + ), |
147 | 180 | ]
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148 | 181 |
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149 | 182 |
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