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jordensjordens
committedOct 10, 2017
kasli: add platform (untested, needs review)
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0.9.20.6.dev
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Diff for: ‎migen/build/platforms/sinara/kasli.py

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from migen.build.generic_platform import *
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from migen.build.xilinx import XilinxPlatform
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_io = [
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("user_led", 0, Pins("Y19"), IOStandard("LVCMOS25")), # LED_USER1
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("clk50", 0, Pins("Y18"), IOStandard("LVCMOS25")),
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("ck_fpgaio", 0,
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Subsignal("p", Pins("W19")),
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Subsignal("n", Pins("W20")),
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IOStandard("LVDS25"),
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),
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("clkrec", 0,
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Subsignal("p", Pins("U20")),
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Subsignal("n", Pins("V20")),
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IOStandard("LVDS25"),
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),
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("serial", 0,
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Subsignal("tx", Pins("V22")),
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Subsignal("rx", Pins("P16")),
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IOStandard("LVCMOS25")
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),
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("clk_sel", 0, Pins("W22"), IOStandard("LVCMOS25")),
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("i2c", 0,
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Subsignal("scl", Pins("U21")),
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Subsignal("sda", Pins("T21")),
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IOStandard("LVCMOS25")
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),
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("spiflash", 0,
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Subsignal("cs_n", Pins("T19")),
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Subsignal("dq", Pins("P22 R22 P21 R21")),
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IOStandard("LVCMOS25")
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),
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("clk_gtp", 0,
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Subsignal("p", Pins("F6")),
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Subsignal("n", Pins("E6")),
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),
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("sfp_gtp", 0,
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Subsignal("txp", Pins("B4")),
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Subsignal("txn", Pins("A4")),
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Subsignal("rxp", Pins("B8")),
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Subsignal("rxn", Pins("A8")),
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),
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("sfp", 0,
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Subsignal("mod_def1", Pins("T3")),
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Subsignal("mod_def2", Pins("U7")),
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Subsignal("los", Pins("U17")),
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Subsignal("mod_present", Pins("U18")),
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Subsignal("rate_select", Pins("P14")),
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Subsignal("tx_disable", Pins("R14")),
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Subsignal("tx_fault", Pins("R18")),
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Subsignal("led", Pins("N17")),
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IOStandard("LVCMOS25")
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),
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# ...
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("sfp", 1,
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# ...
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Subsignal("led", Pins("T18")),
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IOStandard("LVCMOS25")
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),
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# ...
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("sfp", 2,
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# ...
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Subsignal("led", Pins("P20")),
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IOStandard("LVCMOS25")
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),
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("ddram", 0,
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Subsignal("a", Pins(
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"K2 G2 F3 J5 E2 H5 J2 K1 "
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"D1 E1 D2 A1 C2 B1 F4"),
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IOStandard("SSTL15")),
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Subsignal("ba", Pins("H2 J1 G1"), IOStandard("SSTL15")),
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Subsignal("ras_n", Pins("K4"), IOStandard("SSTL15")),
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Subsignal("cas_n", Pins("G4"), IOStandard("SSTL15")),
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Subsignal("we_n", Pins("F1"), IOStandard("SSTL15")),
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# Subsignal("cs_n", Pins(""), IOStandard("SSTL15")),
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Subsignal("dm", Pins("N4 J4"), IOStandard("SSTL15"),
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Misc("DATA_RATE=DDR")),
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Subsignal("dq", Pins(
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"L4 L5 J6 K6 K3 L3 M2 M3 "
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"P1 R1 N2 P2 M5 M6 N5 N6"),
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IOStandard("SSTL15_DCI"),
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Misc("ODT=RTT_40"),
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Misc("DATA_RATE=DDR")),
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Subsignal("dqs_p", Pins("P5 M1"),
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IOStandard("DIFF_SSTL15"),
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Misc("DATA_RATE=DDR")),
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Subsignal("dqs_n", Pins("P4 L1"),
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IOStandard("DIFF_SSTL15"),
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Misc("DATA_RATE=DDR")),
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Subsignal("clk_p", Pins("H3"), IOStandard("DIFF_SSTL15"), Misc("DATA_RATE=DDR")),
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Subsignal("clk_n", Pins("G3"), IOStandard("DIFF_SSTL15"), Misc("DATA_RATE=DDR")),
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Subsignal("cke", Pins("B2"), IOStandard("SSTL15")),
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Subsignal("odt", Pins("H4"), IOStandard("SSTL15")),
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Subsignal("reset_n", Pins("L6"), IOStandard("LVCMOS15")),
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Misc("SLEW=FAST"),
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),
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]
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_connectors = [
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("EEM0", {
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"D0_CC_P": "V4",
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"D0_CC_N": "W4",
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"D1_P": "T1",
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"D1_N": "U1",
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"D2_P": "U2",
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"D2_N": "V2",
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"D3_P": "R3",
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"D3_N": "R2",
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"D4_P": "W2",
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"D4_N": "Y2",
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"D5_P": "W1",
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"D6_P": "Y1",
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"D6_N": "U3",
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"D5_N": "V3",
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"D7_P": "AA1",
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"D7_N": "AB1",
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}),
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# ...
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]
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class Platform(XilinxPlatform):
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default_clk_name = "clk50"
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default_clk_period = 20.0
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def __init__(self):
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XilinxPlatform.__init__(
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self, "xc7a100t-fgg484-2-c", _io, _connectors,
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toolchain="vivado")

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