xilinx: multireg async path constraint

jordens · jordens · commit fccd14e47982 · 2017-10-11T12:23:15.000+02:00
diff --git a/migen/build/xilinx/common.py b/migen/build/xilinx/common.py
@@ -63,6 +63,12 @@ def settings(path, ver=None, sub=None):
 class XilinxMultiRegImpl(MultiRegImpl):
     def __init__(self, *args, **kwargs):
         MultiRegImpl.__init__(self, *args, **kwargs)
+        i = self.i
+        if not hasattr(i, "attr"):
+            i0, i = i, Signal()
+            self.comb += i.eq(i0)
+        i.attr.add("mr_false_path")
+        self.regs[0].attr.add("mr_ff")
         for r in self.regs:
             r.attr.add("async_reg")
             r.attr.add("no_shreg_extract")
diff --git a/migen/build/xilinx/ise.py b/migen/build/xilinx/ise.py
@@ -129,6 +129,8 @@ class XilinxISEToolchain:
         "keep": ("keep", "true"),
         "no_retiming": ("register_balancing", "no"),
         "async_reg": None,
+        "mr_ff": None,
+        "mr_false_path": None,
         "ars_ff1": None,
         "ars_ff2": None,
         "ars_false_path": None,
diff --git a/migen/build/xilinx/vivado.py b/migen/build/xilinx/vivado.py
@@ -75,6 +75,8 @@ class XilinxVivadoToolchain:
         "keep": ("dont_touch", "true"),
         "no_retiming": ("dont_touch", "true"),
         "async_reg": ("async_reg", "true"),
+        "mr_ff": ("mr_ff", "true"),  # user-defined attribute
+        "mr_false_path": ("mr_false_path", "true"),  # user-defined attribute
         "ars_ff1": ("ars_ff1", "true"),  # user-defined attribute
         "ars_ff2": ("ars_ff2", "true"),  # user-defined attribute
         "ars_false_path": ("ars_false_path", "true"),  # user-defined attribute
@@ -91,6 +93,8 @@ def __init__(self):
 
     def _build_batch(self, platform, sources, build_name):
         tcl = []
+        tcl.append("create_property -type bool mr_ff cell")
+        tcl.append("create_property -type bool mr_false_path net")
         tcl.append("create_property -type bool ars_ff1 cell")
         tcl.append("create_property -type bool ars_ff2 cell")
         tcl.append("create_property -type bool ars_false_path net")
@@ -155,6 +159,12 @@ def _convert_clocks(self, platform):
         del self.false_paths
 
     def _constrain(self, platform):
+        # The asynchronous input to a MultiReg is a false path
+        platform.add_platform_command(
+            "set_false_path -quiet "
+            "-through [get_nets -hier -filter mr_false_path] "
+            "-to [get_cells -hier -filter mr_ff]"
+        )
         # The asychronous reset input to the AsyncResetSynchronizer is a false
         # path
         platform.add_platform_command(
