Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Jump to bottom

Upload firmware built by travis to prebuild repository #92

Merged
merged 1 commit into from Oct 7, 2015
Merged

Upload firmware built by travis to prebuild repository #92

merged 1 commit into from Oct 7, 2015

Conversation

sealne
Copy link
Collaborator

@sealne sealne commented Oct 7, 2015

Copy the firmware built by travis to HDMI2USB-firmware-prebuilt

Will need GITHUB_TOKEN set in travis and COPY_REPO_OWNER changed to not copy to my fork

HDMI2USB-firmware-prebuilt will also need tidied up like the forks

@landscape-bot
Copy link

Code Health
Code quality remained the same when pulling 1dc8e47 on sealne:build-copy into f13c17a on timvideos:master.

@landscape-bot
Copy link

Code Health
Code quality remained the same when pulling 11d4635 on sealne:build-copy into f13c17a on timvideos:master.

mithro
mithro reviewed Oct 7, 2015
View reviewed changes
.travis.yml
@@ -1,12 +1,8 @@
sudo: required

sudo: false
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I don't think any of the changes in this file are needed right?

Copy link
Collaborator Author

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

hmm not sure where that came from. nope

mithro
mithro reviewed Oct 7, 2015
View reviewed changes
.travis/run.sh
# Only hdmi2usb is considered usable just now
UNSTABLE_LINK="$BOARD/firmware/unstable"
if [ "$TARGET" = "hdmi2usb" ]; then
# Copy FX2 firmware
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Can we move updating the symlinks to a script which this calls? Something like;

# update-symlink.sh <board> <target> <type> <git revision>
update-symlink.sh atlys hdmi2usb unstable v0.0.0-789-abdc123

Then we can reuse it for updating the stable / testing links too.

@landscape-bot
Copy link

Code Health
Code quality remained the same when pulling 6da19e9 on sealne:build-copy into f13c17a on timvideos:master.

mithro
mithro reviewed Oct 7, 2015
View reviewed changes
.travis/run.sh
git clone https://$GITHUB_TOKEN@github.com/$COPY_REPO_OWNER/$COPY_REPO.git
cd $COPY_REPO
mkdir -p $COPY_DEST
# Not currently built so use .bit instead
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Maybe we should add a "make release" or something which collects all the files into the build/release directory or something?

@landscape-bot
Copy link

Code Health
Code quality remained the same when pulling c31514a on sealne:build-copy into f13c17a on timvideos:master.

@landscape-bot
Copy link

Code Health
Code quality remained the same when pulling 0dcb924 on sealne:build-copy into f13c17a on timvideos:master.

mithro
mithro reviewed Oct 7, 2015
View reviewed changes
.travis/run.sh
# Copy built files
if [ -z $GITHUB_TOKEN ]; then
# Only if run by travis display error
if [ ! -z $TRAVIS_BUILD_NUMBER ]; then
Copy link
Member

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

I think this should also check it isn't a pull request.

mithro added a commit that referenced this pull request Oct 7, 2015
@mithro
Merge pull request #92 from sealne/build-copy
3b0f648 
Upload firmware built by travis into the prebuilt repo.
@mithro mithro merged commit 3b0f648 into timvideos:master Oct 7, 2015
@mithro mithro changed the title Copy firmware built by travis Upload firmware built by travis to prebuild repository Oct 7, 2015
@mithro mithro mentioned this pull request Oct 7, 2015
Closed
mithro added a commit that referenced this pull request Aug 28, 2018
@mithro
Updating submodules.
9916c81 
 * edid-decode changed from dcc8b83 to b2da151
    * b2da151 - edid-decode: add --extract and --check options <Hans Verkuil>
    * e9ffafc - edid-decode: add options and new output formats <Hans Verkuil>
    * ab18bef - edid-decode: add HDMI Forum VSDB fields for HDMI 2.1b <Hans Verkuil>
    * 8c81ccf - Add Samsung UE49KS8005 EDID <Hans Verkuil>
    * 7d8f41f - edid-decode: simplify data block parsing <Hans Verkuil>
    * eee377b - edid-decode: add support for QuantumData 980 EDID file format <Hans Verkuil>
    * 4437dd9 - edid-decode: use const for unsigned char pointers to the EDID <Hans Verkuil>
    * 3b26b8a - edid-decode: fix wrong sample rate unit <Hans Verkuil>
    * 9cb3744 - edid-decode: fix spurious warning about string termination <Hans Verkuil>
    * bc1e846 - edid-decode: reformat to linux kernel coding style <Hans Verkuil>
    * 7684918 - edid-decode: README: updates <Hans Verkuil>
    * 9e59ba9 - edid-decode: update links, add README <Hans Verkuil>
    * 0a454bc - makefile: also honor LDFLAGS <Adam Jackson>

 * litedram changed from 45da365 to 7a5ac75
    * 7a5ac75 - test/test_axi: improve test_axi2native <Florent Kermarrec>
    * d53832d - frontend/axi: split LiteDRAMAXI2Native (write path and read path) <Florent Kermarrec>
    * c846b8b - frontend/axi: add burst support (fixed/incr) <Florent Kermarrec>
    * 3fa77c8 - phy/s6ddrphy: use cwl only for DDR3 <Florent Kermarrec>
    * d9b5bb7 - frontend/bist: support axi with addressing in bytes <Florent Kermarrec>
    * 1370617 - frontend/axi: addressing in bytes not internal dwords <Florent Kermarrec>
    * 06f841d - sdram_init: compute write recovery cycles (we were using max value) <Florent Kermarrec>
    * 53c75f5 - phy/s7ddrphy: add dqs preamble/postamble <Florent Kermarrec>
    * 1c083ea - sdram_init: split init_sequence generation and header geneneration and add .py header genration <Florent Kermarrec>
    *   d7d60cf - Merge branch 'master' of http://github.com/enjoy-digital/litedram <Florent Kermarrec>
    |\
    | *   cd330b4 - Merge pull request #28 from AlphamaxMedia/refactor-master <enjoy-digital>
    | |\
    | | * 818c678 - update module settings to reflect latest changes <bunnie>
    | | * c9b8db5 - i think there's a missing "self" in the params <bunnie>
    * | | ae6f10a - sdram_init: use 60ohm as rtt_wr default value <Florent Kermarrec>
    |/ /
    * | 522cbc9 - frontend: add AXI support for dma and bist <Florent Kermarrec>
    * | 5715734 - frontend: add initial AXI support <Florent Kermarrec>
    * | 97349bc - frontend: rename bridge to wishbone and LiteDRAMWishboneBridge to LiteDRAMWishbone2Native <Florent Kermarrec>
    * | 2b20c11 - add LiteDRAMNativePort to prepare for AXI, change some internals and API of get_port but keep retro-compatibility - LiteDRAMPort -> LiteDRAMNativePort - aw -> address_width - dw -> data_width - cd -> clock_domain <Florent Kermarrec>
    |/
    * 0b6e21a - improve ddr3 electrical settings <Florent Kermarrec>
    * 697eaaf - add board tuning parameters <bunnie>
    * 9a57c4e - phy/s7ddrphy: add DDR3-800 timings <Florent Kermarrec>
    * 9401b92 - move sdram_init to litedram <Florent Kermarrec>
    * 209dc0d - frontend/bist: add dynamic random data and addressing <Florent Kermarrec>
    * b13962c - core/multiplexer: fix 1:1 <Florent Kermarrec>
    * a215ac7 - core/multiplexer: fix count signal width (when max<2) <Florent Kermarrec>
    * ad8438f - core/controller: enable auto_precharge by default <Florent Kermarrec>
    * bba4913 - core/bankmachine: fix auto_precharge (OR on the two buffers for req.lock), don't need to wait for precharge timer to issue auto-precharge <Florent Kermarrec>
    * 2e362ee - core/bankmachine: add auto_precharge setting to enable/disable auto_precharge mode (disabled by defaut) <Florent Kermarrec>
    * 6d23421 - core/bankmachine: rename cmd_bufferPre to cmd_buffer_lookahead <Florent Kermarrec>
    * 23358b5 - core/multiplexer: use self.submodules for timing controllers, fix tFAW count <Florent Kermarrec>
    *   db4ec67 - Merge pull request #24 from JohnSully/AutoPrecharge <enjoy-digital>
    |\
    | * 627cccd - Fix tCCD timing which watched the wrong command <>
    | * 16a852b - Revert "core/refresher: synchronize valid" <>
    | * a4be642 - Fix multiple timings ignored <>
    | *   771ccfd - Merge branch 'master' of https://github.com/enjoy-digital/litedram into AutoPrecharge <>
    | |\
    | |/
    |/|
    * | 6620a91 - core/refresher: synchronize valid <Florent Kermarrec>
    * | b2f1f29 - core/bankmachine: update comments <Florent Kermarrec>
    * | c1b1b07 - core/multiplexer: synchronize ready on tXXDController and tFAWcontroller to improve timings <Florent Kermarrec>
    * | 147466b - multiplexer: create timing controllers module and simplify <Florent Kermarrec>
    * |   eeb57ad - Merge pull request #23 from JohnSully/outoforder <enjoy-digital>
    |\ \
    | | * 3206985 - When auto-precharging assert track_close <>
    | | * 74279ea - Enable auto-precharge <>
    | |/
    | * 03a2ad6 - Ensure out of order is on a per-bank basis <>
    | * 86b3e2d - Add reorder flag to the crossbar <>
    | *   77c513d - Merge upstream.  UNTESTED <>
    | |\
    | |/
    |/|
    * | c28a754 - test: update <Florent Kermarrec>
    * | f7f8452 - core: make rdata_bank optional (break cdc when enabled), fix some usecases <Florent Kermarrec>
    * | 873b970 - frontend: avoid breaking api with last rbank change (use bankbits_max), some cleanup <Florent Kermarrec>
    * |   26f3f01 - Merge pull request #21 from JohnSully/outoforder <enjoy-digital>
    |\ \
    * \ \   74c3c09 - Merge pull request #20 from bunnie/400mhz-pr <enjoy-digital>
    |\ \ \
    | * | | 4823058 - Adding comment to iodelay_tap_average dictionary. <Tim Ansell>
    | * | | d986b60 - add 400MHz tap setting (valid for -3 and -2/2E speed grades) <bunnie>
    * | | | e02a251 - core: make tRRD definition optional and some cosmetic changes <Florent Kermarrec>
    * | | |   5d74eb2 - Merge pull request #19 from JohnSully/timing <enjoy-digital>
    |\ \ \ \
    | |/ / /
    |/| | |
    | | | * 8266a6e - Prevent compilation failures when tRRD == 0 <>
    | | | * ed4be0b - Add write bank to out of order interface <>
    | | |/
    | | * bfa1d6a - remove debug prints <>
    | | * 2fa2a6d - Initial implementation of out of order controller <>
    | | * f1fea6d - Correct tWTR timing: 1) timing starts after the completion of the write burst, 2) We don't need to wait on switches if a write hasn't taken place recently <>
    | |/
    | * eb3f4a0 - fix CAS to CAS timings (needs to account for multiple banks) <>
    | * f0f5e60 - Add tRRD timing checks, and fix tFAW so it considers all banks <>
    |/
    * f0f067f - phy/s7ddrphy: add assert to make sure cmd/dat phases are not identical <Florent Kermarrec>
    * f560b9c - core/bankmachine: remove auto-prechage since introducing a regression, we'll need to do more simulation before integrating <Florent Kermarrec>
    * 2736ebc - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * e830526 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 6d96bcc - core/bankmachine: fix cas_count size when tccd == 1 <Florent Kermarrec>
    * f4ad65e - core/controller: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * eee89d4 - phy/s7ddrphy: add ddr2 support <Florent Kermarrec>
    * c9f2e30 - core/controller: add simulation workaround for 1:2 ddr3 phy <Florent Kermarrec>
    * bd09471 - phy/s7ddrphy: add 1:2 frequency ratio support (BC4 mode for now) <Florent Kermarrec>
    * dec5378 - core/bankmachine: add CAS to CAS support (tCCD) <Florent Kermarrec>
    * 5bc3575 - modules: add retro-compat on MT41J256M16 <Florent Kermarrec>
    * c4dad24 - modules: add description, add speedgrade support and improve tWTR/tFAW definition (in ck, ns or greater of ck/ns) <Florent Kermarrec>
    * 370b05e - core/bankmachine: add Four Activate Window support (tFAW) <Florent Kermarrec>
    * d0ff536 - phy/s7ddrphy: add specific bitslip reset <Florent Kermarrec>
    * 8ba7fca - core/bankmachine: simplify row change detection for auto precharge <Florent Kermarrec>
    * 3255a33 - core/bankmachine: remove specific case for small cmd_buffer_depth <Florent Kermarrec>
    *   d150e3b - Merge pull request #12 from JohnSully/master <enjoy-digital>
    |\
    | * 6b0d5ce - Prevent spurious precharge all commands caused by leaving A10 asserted during precharge <>
    | * d0fcfb1 - Auto-precharge now only fires when it needs to <>
    * | 82b7199 - modules: fix tWTR for DDR3 modules (expressed in sys_clk not ns) <Florent Kermarrec>
    * | f4b92b6 - phy/s7ddrphy: add nphases parameter to get functions <Florent Kermarrec>
    * | d7d5d4a - phy/s7ddrphy: add iodelay_clk_freq parameter <Florent Kermarrec>
    * | f47ddb3 - phy/s7ddrphy: add get_cl_cw function <Florent Kermarrec>
    * | d9da7c5 - phy/s7ddrphy: compute phy settings automatically (based on tck) and add DDR3-1066/1333/1600 support. <Florent Kermarrec>
    * | ba16ebf - phy: add common Series7 PHY (Artix7, Kintex7 & Virtex7) with or without ODELAY. Keep backward compatibility on imports. <Florent Kermarrec>
    * | 2bd7707 - modules: add MT18KSF1G72HZ_1G6 <Florent Kermarrec>
    |/
    * c238149 - phy/kusddrphy: follow more Xilinx recommandations <Florent Kermarrec>

 * liteeth changed from 33afda7 to 24b0d2b
    * 24b0d2b - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 4edba99 - phy: remove s6rgmii (not working correctly). <Florent Kermarrec>
    * 6b872fd - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * 40d91f0 - phy: use rx_dv instead of dv <Florent Kermarrec>
    * ba2fdc5 - README: add 1000BaseX phy <Florent Kermarrec>
    * a2dbdd6 - phy: add a7_1000basex phy (from misoc) <Florent Kermarrec>
    * 95849a0 - core/icmp: use buffered=True on buffer to allow tools to use block rams <Florent Kermarrec>

 * litepcie changed from 8bc328f to a97a691
    * a97a691 - example_designs: update/fix test_regs.py <Florent Kermarrec>
    * d8e602c - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 0ac08e5 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cf0a3e5 - phy/kintex7: fix/update <Florent Kermarrec>
    * 96309fc - core/msi: add transmit_interval parameter to avoid continous retransmission (causing issue with some configurations) <Florent Kermarrec>
    * bb29b81 - core/tlp/reordering: use buffered=True on tag_buffer fifo <Florent Kermarrec>
    * 418e980 - frontend/wishbone: add shadow_base parameter <Florent Kermarrec>
    * 3df4217 - test/test_dma: test both 64b and 128b datapaths and fix writer <Florent Kermarrec>
    * 29a7d16 - test/test_wishbone: test both 64b and 128b datapaths <Florent Kermarrec>
    * 08a8daf - phy/s7pciephy: last is indicated in tuser (and not tlast) for 128 bits datapath <Florent Kermarrec>
    * a20e71b - core/tlp/packetizer/depacketizer: fixes for 128 bits datapath <Florent Kermarrec>
    * 93233fe - frontend/dma: cleanup control bits <Florent Kermarrec>
    * 0540a88 - frontend/dma/writer: avoid stalling pipeline when not enabled <Florent Kermarrec>

 * litesata changed from a559afb to 002cd25
    * 002cd25 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 73cb6fa - example_designs: update <Florent Kermarrec>
    * fd5b38e - examples_designs/platforms: add genesys2 <Florent Kermarrec>
    * 236522b - example_designs/targets/bist: allow cpu_reset with both polarity <Florent Kermarrec>
    *   8bdc28e - Merge pull request #14 from felixheld/crc <enjoy-digital>
    |\
    | * 7f61316 - core/link.py: make CRC calculation more pythonic <Felix Held>
    | * e497f33 - core/link.py: clarify comments in CRC implementation <Felix Held>
    * ec06424 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litescope changed from 9d5e605 to f26e36e
    *   f26e36e - Merge pull request #11 from xobs/add-trigger-depth <enjoy-digital>
    |\
    | * 71ffaa7 - add trigger depth option <bunnie>
    |/
    * bfd06f8 - core: add FSM support (and example) <Florent Kermarrec>
    * 2ca58e4 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * cd63a43 - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * f03345d - software/driver/analyzer: add get_instant_value to get instant value of one signal <Florent Kermarrec>
    * af5bfd1 - software/driver/analyzer: add assertions <Florent Kermarrec>
    * 3efaefa - example_designs: typo <Florent Kermarrec>
    * d919f90 - core: use bits_for(n) instead of max=n on Mux (fix case with only one group of signals) <Florent Kermarrec>
    * 6289e81 - example_designs: demonstrate new features <Florent Kermarrec>
    * e92f0b7 - example_designs/test: cleanup and simplify <Florent Kermarrec>
    * 2233bc2 - core: another cleanup/simplify pass <Florent Kermarrec>
    * a269e67 - software: add rising/falling edge support <Florent Kermarrec>
    * 65b7f08 - core: add full flag for trigger memory <Florent Kermarrec>
    * c0bab06 - core: add sequential-triggering and simplify control <Florent Kermarrec>
    * 26a8b89 - example_designs: update <Florent Kermarrec>
    * 8d4c1dd - core: simplify and run storage in "scope" clock domain to get rid of cd_ratio. <Florent Kermarrec>

 * liteusb changed from 23d6a68 to e841c56
    * e841c56 - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * 7da831d - setup.py: exclude sim, test, doc directories <Florent Kermarrec>

 * litevideo changed from 9b4169d to 7b4240f
    * 7b4240f - setup.py: fix exclude, add example_designs to exclude <Florent Kermarrec>
    * c39517a - setup.py: exclude sim, test, doc directories <Florent Kermarrec>
    * cb8cf59 - Merge pull request #19 from bunnie/terc4-data <enjoy-digital>
    * c704235 - additional debugging on capture <bunnie>
    * eab7078 - add data decoding to Terc4 decoder <bunnie>
    * eb263a8 - add ability to invert the HPD input <bunnie>
    * 7189562 - fix a default edid that works better with rpis <bunnie>
    * 33ed07d - currently commented, but the vestiges of introducing SS clocking <bunnie>
    * 49adfb4 - change the default edid to one that advertises a proper 1080p mode <bunnie>
    * 19437d0 - add dvimode/hdmimode setting bit for DE detection <bunnie>
    * 449d339 - add decoding of terc4 islands, proper DE extraction on HDMI <bunnie>
    * 447726f - add RGB input mode support to hdmi in <bunnie>
    * f5842bc - add some code to allow frame start offset trimming for genlock <bunnie>
    * 12aa4f9 - clarify the self vs local signal settings for easier probing <bunnie>
    * 9b3c93e - move BUFR->BUFG <bunnie>
    * 166dc57 - fix typo on naming <bunnie>
    * 33f8833 - change the genlock method from pulse to wholesale signal change <bunnie>
    * 784cc8c - changes needed for a basic genlock <bunnie>

 * litex changed from v0.1-319-gb7f7c8d1 to v0.1-423-g7a14b75c
    *   7a14b75c - Merge pull request #93 from phlipped/master <Tim Ansell>
    |\
    | * 8b51c445 - Fix URL for liteUSB <phlipped>
    |/
    *   0074bb88 - Merge pull request #91 from cr1901/ignore-fix <Tim Ansell>
    |\
    | * dd480eb7 - .gitignore: litex/build contains valid source, so exclude from .gitignore. <William D. Jones>
    * |   ff908e40 - Merge pull request #92 from cr1901/l2-gate <Tim Ansell>
    |\ \
    | * | 3146109a - software/bios: Gate flush_l2_cache() if L2 Cache isn't present. <William D. Jones>
    | |/
    * | 759e7d4d - bios/sdram: improve/simplify read window selection <Florent Kermarrec>
    * | 09776b77 - sim: run as root only when needed (ethernet module present) <Florent Kermarrec>
    * | 06e835a3 - builder: change call to get_sdram_phy_c_header and also pass timing_settings <Florent Kermarrec>
    * | ee26f8c5 - soc_sdram: cosmetic <Florent Kermarrec>
    * | 2db5424a - soc_sdram: vivado is now able to implement the l2_cache correctly (tested with vivado 2017.2 and >) <Florent Kermarrec>
    * | 45e9a42c - soc_core: add cpu_endianness <Florent Kermarrec>
    * | 3877d0f1 - builder: get_sdram_phy_header renamed to get_sdram_phy_c_header <Florent Kermarrec>
    * | c64e44ef - soc_sdram: use new LiteDRAMWishbone2Native and port.data_width <Florent Kermarrec>
    * | 2eeccc50 - vexriscv: update <Florent Kermarrec>
    * | eecc6f68 - soc/integration: move sdram_init to litedram <Florent Kermarrec>
    |/
    * 077f9391 - Vexriscv: update csr-defs.h <Florent Kermarrec>
    * 4225c3b8 - update Vexriscv <Florent Kermarrec>
    * 95479385 - bios/sdram: changes to ease manual read window selection <Florent Kermarrec>
    * a760322f - litex_server: allow multiple clients to connect to the same server <Florent Kermarrec>
    * 8a69a47e - cpu/lm32: add minimal variant with no i/d cache, pipelined barrel shifter and multiplier (useful to build SoC on small FPGAs like ice40) <Florent Kermarrec>
    * cb5b4ac4 - bios/boot: flush all caches before running from ram <Florent Kermarrec>
    * 650ac186 - sim/verilator: catch ctrl-c on exit and revert default termios settings <Florent Kermarrec>
    * 0831ad54 - cpu_interace: use riscv64-unknown-elf if available else riscv32-unknown-elf <Florent Kermarrec>
    * 1610a7f3 - bios/sdram: fix read_level_scan result <Florent Kermarrec>
    *   e07ca057 - Merge pull request #86 from pgielda/patch-1 <enjoy-digital>
    |\
    | * 3c7890cd - Fix generating csr.csv file <Peter Gielda>
    |/
    * 9fa234da - soc/intergration/cpu_interface: typo <Florent Kermarrec>
    * 22f645ad - bios/main: use edata instead of erodata <Florent Kermarrec>
    * 580efecc - picorv32: add reset signal <Florent Kermarrec>
    * 0429ee9f - soc/software/bios: add reboot command <Florent Kermarrec>
    * da751598 - soc/integration/soc_core: add Controller with reset, scratch and bus_errors registers <Florent Kermarrec>
    * 8ba56252 - soc/interconnect/wishbone: add Timeout to avoid stalling bus when not responding and generate error. <Florent Kermarrec>
    * c0989f65 - soc/cores/cpu: add reset signal <Florent Kermarrec>
    *   380f8b96 - Merge pull request #81 from xobs/vexriscv-to-wishbone <enjoy-digital>
    |\
    | * fb145dac - tools: remove vexriscv_debug <Sean Cross>
    | * f17b8324 - vexriscv: reset wishbone bus on CPU reset <Sean Cross>
    | * c87ca4f1 - vexriscv: put debug bus directly on wishbone bus <Sean Cross>
    |/
    * 20d6fcac - add litex_setup script to clone and install Migen, LiteX and LiteX's cores <Florent Kermarrec>
    * 8a311bf4 - build/generic_platform: use list for sources instead of set <Florent Kermarrec>
    * df7e5dbc - bios/sdram: add ERR_DDRPH_BITSLIP constant and some cleanup <Florent Kermarrec>
    * 1564b440 - soc/integration/soc_sdram: add assertion on csr_data_width since BIOS only support SDRAM initialization for csr_data_width=8 <Florent Kermarrec>
    * ae62fe07 - setup.pu: fix exclude <Florent Kermarrec>
    * c314193c - boards/plarforms/genesys2: replace user_dip_sw with user_sw <Florent Kermarrec>
    * 10dd55fd - boards/platforms/genesys2: add minimum HPC connectors to be able to test SATA, add programmer parameter <Florent Kermarrec>
    * b19844d1 - setup.py: exclude test, sim, doc directories <Florent Kermarrec>
    * 85308672 - software/bios/linker: revert data section since required by RISC-V compiler <Florent Kermarrec>
    *   55dd58b0 - Merge pull request #80 from xobs/fix-vexriscv-csr-read <enjoy-digital>
    |\
    | * 41a9e7d9 - vexriscv_debug: use csr read()/write() accessors <Sean Cross>
    * | 7ecdcaca - soc/integration/sdram_init: use fixed burst_length for each memtype (even in 1:2, use BL8 for DDR3 since BL4 is not efficient) <Florent Kermarrec>
    * | a4caa896 - targets/nexys_video: remove read leveling constants (now automatic) <Florent Kermarrec>
    * | d8250041 - targets/nexys4ddr: s7ddrphy now supports ddr2, working <Florent Kermarrec>
    * | 4f1274e6 - bios/sdram: improve bitslip selection when window can't be optimal (not enough taps for a full window) <Florent Kermarrec>
    * | 7dbd85a8 - soc/cores/uart: rename UARTMultiplexer to RS232PHYMultiplexer. UARTMultiplexer now acts on serial signals (tx/rx) <Florent Kermarrec>
    * | ef1c7784 - soc_core: add csr_expose parameter to be able to expose csr bus (useful when design is integrated in another) <Florent Kermarrec>
    |/
    * f9104b20 - bios/sdram: improve read leveling (artix7 read-leveling is now done automatically at startup) <Florent Kermarrec>
    * c84e189d - bios/sdram: fix compilation with no write leveling <Florent Kermarrec>
    *   b062d4dd - Merge pull request #79 from xobs/fix-vexriscv-data-read <enjoy-digital>
    |\
    | * be8eb5ff - vexriscv: debug: fix reading DATA register <Sean Cross>
    |/
    *   e35be26e - Merge pull request #78 from xobs/vexriscv_debug_bridge <enjoy-digital>
    |\
    | * 6bc9265c - setup: add vexriscv_debug to list of entrypoints <Sean Cross>
    | * 45a649be - tools: vexriscv_debug: add debug bridge <Sean Cross>
    |/
    * c821a0fe - cores/cpu/vexriscv: create variants: None and "debug", some cleanup <Florent Kermarrec>
    * 59fa7159 - core/cpu/vexriscv/core: improve indentation <Florent Kermarrec>
    *   6068f6ce - Merge pull request #77 from xobs/debug-vexriscv-enjoy <enjoy-digital>
    |\
    | * 32d5a751 - soc_core: uart: add a reset line to the UART <Sean Cross>
    | * 1ef127e0 - soc: integration: use the new cpu_debugging flag for vexriscv <Sean Cross>
    | * e7c762c8 - soc: vexriscv: add cpu debug support <Sean Cross>
    | * 2024542a - vexriscv: verilog: pull debug-enabled verilog <Sean Cross>
    * | 11e84915 - platforms/arty_s7: keep up to date with Migen <Florent Kermarrec>
    * | d35dc5cd - platforms/arty: merge with Migen <Florent Kermarrec>
    |/
    * fa021566 - platforms/kc705: keep up to date with Migen <Florent Kermarrec>
    * b9f3b49c - platforms/de0nano: keep up to date with Migen <Florent Kermarrec>
    * 1628c36a - README/boards: add precision on Migen's platforms <Florent Kermarrec>
    * df99cc66 - bios/sdram: also check for last read of scan to choose optimal window <Florent Kermarrec>
    * 8ce7fcb2 - bios/main: add cpu frequency to banner <Florent Kermarrec>
    * 477d2249 - bios/sdram: check for optimal read window before doing read leveling, increment bitslip if not optimal. <Florent Kermarrec>
    * 9e737d3c - soc/cores/code_8b10b: update (from misoc) <Florent Kermarrec>
    * d58eb4ec - bios/sdram: use new phy, improve scan, allow disabling high skew <Florent Kermarrec>
    * 692cb142 - software/bios: fix picorv32 boot_helper <Florent Kermarrec>
    * b5ee110e - bios/sdram: add write/read leveling scans <Florent Kermarrec>
    * 34b2bd0c - boards: add genesys2 (platform with clk/serial/dram/ethernet + target) <Florent Kermarrec>
    * 8edc659d - soc_core: remove assert on interrupt (added to catch design issues, but too restrictive for some usecases) <Florent Kermarrec>
    * 2c13b701 - soc/integration/cpu_interface: add shadow_base parameter <Florent Kermarrec>
    *   78639fa9 - Merge pull request #75 from xobs/bios-windows-build <enjoy-digital>
    |\
    | * 74449929 - soc: bios: fix windows build <Sean Cross>
    |/
    * 18f86881 - targets: change a7/k7ddrphy imports to s7ddrphy <Florent Kermarrec>
    * 3e723d15 - soc/cores/cpu: add add_sources static method <Florent Kermarrec>
    *   c534250c - Merge pull request #72 from bunnie/fix_riscv_boothelper <enjoy-digital>
    |\
    | * 7353197e - fix the vexriscv boot helper <bunnie>
    |/
    *   5ab4282e - Merge pull request #71 from DeanoC/master <enjoy-digital>
    |\
    | * 34a93034 - Fix for missing connectors for arty boards <Deano Calver>
    |/
    * e7d1683e - litex_term: cleanup getkey and revert default settings on KeyboardInterrupt <Florent Kermarrec>
    * 06162b61 - README: add list of supported CPUs/Cores and add link to tutorials <Florent Kermarrec>
    * 6854c7f5 - soc/integration/cpu_interface: use riscv64 toolchain instead of riscv32 (prebuild toolchain for windows can be found at http://gnutoolchains.com/) <Florent Kermarrec>
    * 66229c8c - add VexRiscv support (imported/adapted from misoc) <Dolu1990>
    * f60da4a5 - add VexRiscv submodule <Florent Kermarrec>
    * d149f386 - allow multiple riscv32 softcores (use picorv32 cpu_type instead of riscv32) <Florent Kermarrec>
    * c3652935 - build: use our own fhdl/verilog code (needed to avoid combinatorial loop in simulation) <Florent Kermarrec>
    * 121eaba7 - soc/intergration/soc_core: don't delete uart/timer0 interrupts <Florent Kermarrec>
    * 39ffa532 - xilinx/programmer: fix programmer <Florent Kermarrec>
    * c001b8ea - build/xilinx/vivado: add vivado ip support <Florent Kermarrec>
    * 43f8c230 - soc_core: uncomment uart interrupt deletion <Florent Kermarrec>
    * d7c74746 - gen/sim: fix import to use litex simulator instead of migen simulator <Florent Kermarrec>

 * migen changed from 0.6.dev-99-g881741b to 0.6.dev-162-ga6082d5
    * a6082d5 - added support for qm_xc6slx16_sdram <Daniel Kucera>
    * 2d37c78 - add indexed part select support <Robin Ole Heinemann>
    * 5fe1bfe - build/platforms: Add tinyfpga_a platform. (#111) <William D. Jones>
    * 307e752 - fhdl.specials: add reset_i argument to TSTriple. <whitequark>
    * 18274c3 - build.lattice: fix IcestormTristate override for 1-bit signals. <whitequark>
    * e07c1c5 - build.lattice: add IcestormTristate override. <whitequark>
    * 0509a7b - fhdl.verilog: make convert() idempotent. <whitequark>
    * 5dd4efa - genlib.fifo: add read() and write() methods, for simulation. <whitequark>
    * 4e4833d - sayma_amc: AMC_MASTER_AUX_CLK is in a 3.3V bank, needs LVDS_25, cannot use termination <Sebastien Bourdeauducq>
    * 47f4c59 - typo <Sebastien Bourdeauducq>
    * 870935d - sayma_amc: add AMC_MASTER_AUX_CLK <Sebastien Bourdeauducq>
    * bef9dea - platform: support recursive connector pins <Sebastien Bourdeauducq>
    * cb171af - platform: support adding connectors <Sebastien Bourdeauducq>
    * 26d77fe - xilinx/ise: Add Cygwin path to Windows conversion in xst files (#88) <William D. Jones>
    * 1ec3ea9 - sayma_rtm: add hmc7043_gpo <Sebastien Bourdeauducq>
    * b515b0e - platforms/arty_a7: merge with LiteX's platform, remove the FIXMEs <Florent Kermarrec>
    * 9d3db58 - Sayma AMC: add SYSCLK1_300 <Thomas Harty>
    * daf6f5d - sayma: add adc_sysref pins <Sebastien Bourdeauducq>
    * dcfec40 - sayma_amc: fix raw RTM GTH pair polarities <Sebastien Bourdeauducq>
    * 7823da4 - sayma_amc: add raw RTM GTH pairs <Sebastien Bourdeauducq>
    * df0ce4a - Update version in setup.py. <whitequark>
    * e4e92dc - Fixed case of xadc to match kc705. <Caleb Jamison>
    * 84186ca - Changed ck_io to name pins, add xadc. <Caleb Jamison>
    * c2480c9 - Removed _ from spiflash_4x <Caleb Jamison>
    * fd7ce92 - Moved pmods to _connectors, removed _1x from spiflash <Caleb Jamison>
    * 2896306 - Changed spiflash_1x to spiflash in _io list. <Caleb Jamison>
    * ede1c9e - Add _connectors to constructor <Caleb Jamison>
    * 20d28d4 - Removed extra field from _connector list <Caleb Jamison>
    * 02e80df - Add chipkit io to _connector list <Caleb Jamison>
    * 1eeb38d - Fixed missing parens, extra spaces <Caleb Jamison>
    * 0dd85cd - Split pmods to _connectors, checked against litex <Caleb Jamison>
    * 04a9914 - Arty A7 platform <Caleb Jamison>
    * 07c46f5 - Support for AFC 3v1 <Mikołaj Sowiński>
    * 9929b23 - sayma_amc: fix 19e82b7 syntax <Robert Jördens>
    * 19e82b7 - sayma_amc: diff term lvds inputs <Robert Jördens>
    * a51a5f6 - sayma: use LVCMOS18 for serwb <Sebastien Bourdeauducq>
    * 34a3c62 - sayma_rtm: LVDS_18 is called LVDS <Sebastien Bourdeauducq>
    * e5cabe1 - sayma_rtm: fix I/O bank voltages <Sebastien Bourdeauducq>
    * 5947224 - sayma_rtm: add ref_lo_clk_sel <Robert Jördens>
    * 4cb07f1 - bitcontainer: slices are unsigned <Robert Jördens>
    * ca28f4e - platforms/sayma_amc/serwb: use DIFF_TERM_ADV=TERM_100 <Florent Kermarrec>
    * 6425844 - revert genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 33bb06a - genlib/cdc: add optional master parameter to ElasticBuffer to allow sharing write reset between ElasticBuffers <Florent Kermarrec>
    * 48f2b92 - doc/fhdl: use correct syntax for code block. <whitequark>
    * e66f2df - Fix documentation link in README. <whitequark>
    * 2423404 - fhdl.verilog: fix nondeterminism in _printcomb. <whitequark>
    * 0aa76fa - build/platforms: Add Arty S7 platform. <William D. Jones>
    * 19ca7d8 - platforms/tinyfpga_b: Add default serial mapping. <William D. Jones>
    * cba5bea - sayma_amc/rtm: use DIFF_TERM=TRUE on serwb lvds inputs <Florent Kermarrec>
    * 9bc084a - Update .gitignore. <whitequark>
    * d46aa13 - fhdl.verilog: do not initialize combinatorial regs. <whitequark>
    * 02bccef - Fix breakage introduced in 2220222. <whitequark>
    * d667233 - LatticeIceStormToolchain: pass --no-promote-globals to arachne-pnr. <whitequark>
    * 2220222 - genlib.cdc.MultiReg: allow specifying reset value for registers. <whitequark>
    * 5c2c144 - sayma_rtm: enable OVERTEMPPOWERDOWN and use options from artiq <Robert Jordens>
    * 24d0e95 - samya_amc: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * a32a0f7 - kasli: enable OVERTEMPPOWERDOWN <Robert Jordens>
    * 81d0be3 - DDROutputImplS7: make it SAME_EDGE and fix it <Robert Jordens>
    * 4039322 - kasli: mark negative polarity of mod_present on v1.1 <Sebastien Bourdeauducq>
    * b50e224 - Add DE0-Nano-SoC (aka Atlas-SoC) platform (#96) <Adam Greig>
    * c14a1e4 - Add MyStorm BlackIce I and II platforms (#95) <Adam Greig>
    * f4180e9 - vivado: print short timing info after phys_opt_design <Sebastien Bourdeauducq>
    * c65a2f3 - vivado: run phys_opt_design after routing <Sebastien Bourdeauducq>

Full submodule status
--
 b2da1516df3cc2756bfe8d1fa06d7bf2562ba1f4 edid-decode (remotes/origin/HEAD)
 a628956da7dc794e6e3c95b31ff9ce3af58bc763 flash_proxies (remotes/origin/HEAD)
 7a5ac75e2295dcf15f83df966244f30154a8f662 litedram (remotes/origin/HEAD)
 24b0d2b8c2cfcf96a8c6cb56ec01af9a56952aad liteeth (remotes/origin/HEAD)
 a97a6910cbebfb4c068a178139df7b9a9c72168f litepcie (remotes/origin/HEAD)
 002cd25e7fd2a60b4dcf1ce829731b9cf5c2f744 litesata (remotes/origin/HEAD)
 f26e36ef23170002af8ab1461ba39209e531b6cb litescope (remotes/origin/HEAD)
 e841c5646c17ecbf07642c69c16c6c7c45e55475 liteusb (remotes/origin/HEAD)
 7b4240f9b3d6b7e69e5fe9dbaf50e117bd0ca704 litevideo (remotes/origin/HEAD)
 7a14b75cd676e9328063abc1fcdc6fcd4fc6c5ef litex (v0.1-423-g7a14b75c)
 a6082d56ccc615229bd3b5205f5b7207c14dca01 migen (0.6.dev-162-ga6082d5)
mithro pushed a commit that referenced this pull request Nov 17, 2018
@cr1901
targets/ice40_up5k_b_evn: Enable CAS module. Closes #92.
000cf4c
mithro added a commit that referenced this pull request Jan 30, 2020
@mithro
Updating submodules.
3a9127d 
 * edid-decode changed from 42f5fa4 to 3a6108a
    * 3a6108a - edid-decode: Add Dell UP3218K DP tiled edid <Clint Taylor>
    * ad20c30 - edid-decode: improve DisplayID 1.2/3 parsing <Hans Verkuil>
    * 31a3417 - edid-decode: add warn() function <Hans Verkuil>
    * 8752afd - edid-decode: improve some of the texts <Hans Verkuil>
    * 8f7bb1f - edid-decode: improve readability of output <Hans Verkuil>
    * dc8afbf - edid-decode: add new HDMI 2.1 Amendment A1 and HDR10+ support <Hans Verkuil>
    * 44d1587 - edid-decode: add more EDIDs <Hans Verkuil>
    * 7d26052 - edid-decode: improve "Invalid Detailed Timings" message <Hans Verkuil>
    * 0da30bd - edid-decode: Avoid division by zero <Breno Leitao>
    * ea15b91 - edid-decode: add ELO 4600L EDID <Hans Verkuil>
    * 7696439 - Add LG 32UD99-W edid from the DP (USB-C) input <Hans Verkuil>
    * 0932dee - Add LG 32UD99-W edid from the HDMI input <Hans Verkuil>
    * 3bd8bbe - Add EDID for LG OLED55E6V <Hans Verkuil>
    * d5fb521 - Add an EDID for the Samsung UE48JU7090 <Hans Verkuil>

 * flash_proxies changed from 1c21ee4 to 01d8f81
    * 01d8f81 - remove bscan_spi_xcku040-sayma <Sebastien Bourdeauducq>

 * litedram changed from 6c53996 to 401554f
    *   401554f - Merge pull request #92 from gsomlo/gls-assert-width <enjoy-digital>
    |\
    | * 7356d3b - frontend/wishbone: add base_address param. to LiteDRAMWishbone2Native <Gabriel Somlo>
    | * 24203cf - frontend/axi: add assertion on matching axi, native port data_width <Gabriel Somlo>
    |/
    * d84e1b4 - frontend/axi: add assert on axi.address_width and base_address <Florent Kermarrec>
    * 1d037d2 - frontend/axi: add base_address parameter to LiteDRAMAXI2Native <Florent Kermarrec>
    * 5d1a984 - core: add LiteDRAMCore (ControllerInjector from LiteX) <Florent Kermarrec>
    * d647abd - gen: fix with_wishbone <Florent Kermarrec>
    * db97203 - gen: use SoCCore with_wishbone parameter, do more replace in yml files before passing config to LiteDRAMCore <Florent Kermarrec>
    * adf481f - gen: disable peripherals that are not used when cpu_type is None <Florent Kermarrec>
    * 2331919 - gen: change CSR config names, switch to csr_expose/csr_align <Florent Kermarrec>
    * da408a3 - gen: fix default csr_port_align value <Florent Kermarrec>
    * bac66aa - gen: In conjunction with the corresponding changes in litex itself, this will allow us to generate a more useful standalone litedram core. <Benjamin Herrenschmidt>
    * afbf709 - We had the address and data bus sizes mixed up <Benjamin Herrenschmidt>
    * d93dded - frontend/wishbone: add data_width assertions <Florent Kermarrec>
    * f586aad - phys: improve presentation (add separators, better indent) <Florent Kermarrec>
    * 783258c - phys: use dfi instead if self.dfi internally <Florent Kermarrec>
    * 59c1289 - phy/usddrphy: move DDR4DFIMux to dfi.py <Florent Kermarrec>
    * f861d99 - core/refresher: improve naming/parameters of refresh postponing <Florent Kermarrec>
    * dc1bb53 - phys: move get_cl_cw/get_sys_latency/get_sys_phases helpers to common <Florent Kermarrec>
    * 509f606 - README: add periodic refresh/ZQ short calibration. <Florent Kermarrec>
    * 40b4c62 - test/test_init: fix <Florent Kermarrec>
    * 5b48eb2 - test/test_init: delete generated file <Florent Kermarrec>
    * 188b6a8 - add ZQ periodic short calibration support (default to 1s) <Florent Kermarrec>
    * 6e176d4 - init: split by memtype <Florent Kermarrec>
    * 0b24b81 - test: add test_init with sdr/ddr3/ddr4 references <Florent Kermarrec>
    * bf5883c - rename sdram_init to init <Florent Kermarrec>
    * 23ccdc9 - modules: add DDR3 MT8KTF51264 SO-DIMM <Florent Kermarrec>
    * d37a30e - litedram_gen: add wishbone user port support <Florent Kermarrec>
    * b6a0eff - frontend/wishbone: split control/data paths (to avoid data muxes) <Florent Kermarrec>
    * 6497343 - frontend/wishbone: remove IDLE fsm state <Florent Kermarrec>
    * 00ecb87 - gen: add separators <Florent Kermarrec>
    * a782eb5 - test/test_examples: adapt for travis <Florent Kermarrec>
    * f678efa - travis: add pyyaml <Florent Kermarrec>
    *   8861d80 - Merge pull request #91 from sd-fritze/master <enjoy-digital>
    |\
    | * fe2cc94 - modules: Add support for Micron MT47H32M16 DDR2 RAM <gruetzkopf>
    |/
    * a23b9e7 - core/refresher: set cmd.valid to 0 when sequencer done <Florent Kermarrec>
    * 12ddc13 - litedram/gen: add description and switch to argparse <Florent Kermarrec>
    * 2bdeda0 - move standalone core generation to litedram package and make it usable externally <Florent Kermarrec>
    * 0dde125 - examples/litedram_gen: fix #!/usr/bin/env python3 location <Florent Kermarrec>
    * 602ff8b - examples: switch to YAML config files <Florent Kermarrec>
    * fb28f79 - core/refresher: remove load/load_count on RefreshTimer (not used) <Florent Kermarrec>
    * 1c69f49 - core/controller: allow user provided Refresher <Florent Kermarrec>
    * b64daba - core/controller: add separators, ease readibility <Florent Kermarrec>
    * 338d18d - core/refresher: add capability to accumulate N refreshs and execute the N refreshs together <Florent Kermarrec>
    * 818c4ca - core/refresher: another cleanup pass <Florent Kermarrec>
    * 80c8ecf - core/multiplexer: rewrite arbiter comment <Florent Kermarrec>
    * 37db416 - core/refresher: another cleanup pass <Florent Kermarrec>
    * f0592ff - core/refresher: add comments <Florent Kermarrec>
    * de38b52 - core/refresher: rename RefreshGenerator to RefreshSequencer and simplify <Florent Kermarrec>
    * 8573c22 - phy/gensdrphy: add assertions on length of pads.dq/pads.dq <Florent Kermarrec>

 * liteeth changed from ad187d3 to 4d9e74f
    * 4d9e74f - phy/usrgmii: cleanup (style, indent) <Florent Kermarrec>
    * 4bc79ce - examples/targets/core: update <Florent Kermarrec>
    * cd0eaa9 - Merge pull request #19 from jersey99/master <enjoy-digital>
    * 59e0460 - Adds RGMII phy support for Xilinx Ultrascale Devices. Hardware tested on HTG-940 <Vamsi K Vytla>

 * litepcie changed from 71c9a3a to 47e76f4
    * 47e76f4 - example/dma: keep up to date with litex <Florent Kermarrec>
    * 7f9367c - example/make: keep up to date with litex <Florent Kermarrec>
    * c6a536a - frontend/dma: add optional underflows/overflows monitoring, rename tx_fifo/rx_fifo to reader_fifo/writer_fifo <Florent Kermarrec>
    * 6bb4a60 - frontend/dma/buffering: expose fifo levels to CSRs <Florent Kermarrec>

 * litescope changed from 9e3b9d8 to 7a9fa9d
    * 7a9fa9d - core: use new CSRStatus.we signal to speed-up Storage upload (>10x speedup over ethernet) <Florent Kermarrec>
    * 284253d - core: add csr_csv parameter and export csv_csv on do_exit <Florent Kermarrec>
    * 69a8df0 - Merge pull request #14 from DurandA/master <enjoy-digital>
    * 06cac3a - Use cpu instead of cpu_or_bridge in examples <Arnaud Durand>

 * litevideo changed from 98e145f to 49bafa4
    * 49bafa4 - input/dma: no longer use aligment_bits of CSRStorage <Florent Kermarrec>

 * litex changed from v0.1-1099-ge637aa65 to v0.1-1333-ga54b80b9
    * a54b80b9 - targets: use type="io" instead of io_region=True <Florent Kermarrec>
    * a0c0a6fd - integration/SoCMemRegion: use type instead of io_region/linker_region and export type to csv/json <Florent Kermarrec>
    * 9fcf2973 - soc_core: add check_regions_overlap method, add linker_region support (overlap is not checked on linker_regions) <Florent Kermarrec>
    * 4014fbff - soc_core/add_memory_region: fix memory overlap detection <Florent Kermarrec>
    * 650df0eb - test/test_targets: skip Minerva test on Travis-CI, remove commented tests <Florent Kermarrec>
    * ab8af282 - cpu/minerva: elaborate from nmigen sources during build, enable hardware multiplier <Florent Kermarrec>
    *   4cc40aad - Merge pull request #286 from gsomlo/gls-timingstrict <enjoy-digital>
    |\
    | * 49372852 - build/lattice/trellis: optionally allow failure if p&r timing not met <Gabriel Somlo>
    |/
    *   b6d35c92 - Merge pull request #283 from kbeckmann/kbeckmann/bios_increment_address <enjoy-digital>
    |\
    | * ef78ae95 - bios: Increment address when writing to flash <Konrad Beckmann>
    * | 683e0668 - build/lattice/trellis: use --timing-allow-fail to allow generating bistream when timings are not met <Florent Kermarrec>
    * | 4cf346a1 - soc/cores/icap/ICAPBitstream: always keep fifo.source.ready to 1 <Florent Kermarrec>
    * |   39862f06 - Merge pull request #282 from antmicro/icapbitstream_fixes <enjoy-digital>
    |\ \
    | * | 8b5da9c6 - cores/icap/ICAPBitstream: add source ready signal. <Jan Kowalewski>
    |/ /
    * | 626533ce - soc/integration/__init__: remove imports (not used and causing issues <Florent Kermarrec>
    * | 675b4552 - build: always use platform.add_source and avoid manipulate platform.sources directly <Florent Kermarrec>
    * | 43f5d1ef - build/generic_platform: replace set with list for sources/verilog_include_paths <Florent Kermarrec>
    * | 97a77b95 - cores/icap/ICAPBitstream: simplify, add icap_clk_div parameter, describe how to use it. <Florent Kermarrec>
    * | 98c224be - build/generic_platform: keep language to None if None after tools.language_by_filename <Florent Kermarrec>
    * | 14dae8bd - soc_core: fix default --uart_name <Florent Kermarrec>
    * | ba264418 - integration/soc_core: expose more SoC parameters <Florent Kermarrec>
    * |   23d83961 - Merge pull request #280 from kbeckmann/picorv32_typo <Tim Ansell>
    |\ \
    | |/
    |/|
    | * 0e467168 - picorv32: Fix minimal variant params <Konrad Beckmann>
    |/
    * ef504f62 - soc_core: fix soc_core_argdict <Florent Kermarrec>
    * cd8213b9 - cpu/lm32: add missing buses <Florent Kermarrec>
    * 5a035875 - soc_core/soc_core_argdict: use inspect to get all parameters and simplify <Florent Kermarrec>
    * 96c369f3 - integration: simplify cpu buses auto-conversion (always use Converter, thanks gsomlo) <Florent Kermarrec>
    * 29e51f5e - interconnect/wishbone: fix Converter case when buses are identical <Florent Kermarrec>
    * ae9c25b7 - platforms/versa_ecp5: add serdes refclk/sma <Florent Kermarrec>
    * 9a829338 - cpu/rocket: expose 64-bit buses (use automatic down-conversion of SoCCore) <Florent Kermarrec>
    * ca81cc20 - soc_core: add automatic down-conversion of CPU buses to 32-bit (if needed) <Florent Kermarrec>
    * 03faf06c - soc/interconnect/axi: re-align to improve readability <Florent Kermarrec>
    * 7dea9afd - software/bios: simplify banners <Florent Kermarrec>
    * 6bd18893 - cpu/picorv32: remove obsolete comment <Florent Kermarrec>
    * 28517d20 - cpu/picorv32: use a single idbus <Florent Kermarrec>
    * 5daf1a22 - cpu: cleanup/re-align <Florent Kermarrec>
    * 467d35ed - cpu/rocket: rename ibus/dbus to mem_wb/mmio_wb and add size suffix <Florent Kermarrec>
    * 1045cda3 - cpu: add buses list and use it in soc_core to add bus masters <Florent Kermarrec>
    * 42ccc91f - integration: move soc constants to soc.h of csr.h <Florent Kermarrec>
    * ed3c53d7 - build/generic_platform: only add sources if language is not None <Florent Kermarrec>
    * f3ba0788 - xilinx/vivado: replace "xy" == language with language == "xy" <Florent Kermarrec>
    *   17756f63 - Merge pull request #277 from railnova/feature/vivado_sysverilog_support <enjoy-digital>
    |\
    | * f2369a4c - Add system Verilog support for the Vivado builder <Martin Cornil>
    * | b2519482 - integration/soc_zynq: shadow_base no longer recommended (replace with io_regions) <Florent Kermarrec>
    * | 496ba7e5 - bios/main: use same banner than README (MiSoC cited in README/LICENSE) <Florent Kermarrec>
    * | 840f01b6 - software/bios: don't show peripherals init banner if nothing to init, add Ethernet init printf <Florent Kermarrec>
    |/
    *   37531cec - Merge pull request #276 from gsomlo/gls-rocket-map <enjoy-digital>
    |\
    | * f8f643a0 - cpu/rocket: swap main_mem and io regions <Gabriel Somlo>
    |/
    * b627a8fe - cpu: add default io_regions to CPUNone (all address range can be used as IO) <Florent Kermarrec>
    *   cc245fc8 - Merge pull request #275 from pcotret/patch-1 <enjoy-digital>
    |\
    | * e923a88d - Update README (related to issue #273) <Pascal Cotret>
    * | a6b3aa3c - soc_core: improve check_io_region error message <Florent Kermarrec>
    * | dc656d48 - targets/sim: switch from shadow_base to io_regions <Florent Kermarrec>
    * | 10146abf - cpu/rocket: move csr to IO region <Florent Kermarrec>
    * | 7f1d4623 - build/xilinx/vivado: fix default synth-mode <Florent Kermarrec>
    * | a4ef9b29 - soc_core/cpu: add io_regions and deprecate shadow_base (with API retro-compat) <Florent Kermarrec>
    |/
    *   e8b90e80 - Merge pull request #274 from gsomlo/gls-shadow-base <enjoy-digital>
    |\
    | * 53777391 - builder: use the SoC's existing shadow base with get_csr_header() <Gabriel Somlo>
    |/
    * 92975b13 - targets/arty: allow setting synth-mode to yosys with command line: --synth-mode=yosys <Florent Kermarrec>
    * 4a1cefe9 - build/xilinx/vivado: add vivado_build_args/vivado_build_argdict for yosys synthesis mode <Florent Kermarrec>
    * 3e22d4b9 - xilinx/common: be sure language is not vhdl when yosys synthesis is used <Florent Kermarrec>
    * 975bd9be - cpu/vexriscv: use specific mem_map for linux variant <Florent Kermarrec>
    *   2dfe7441 - Merge pull request #271 from gsomlo/gls-yosys-nowidelut <enjoy-digital>
    |\
    | * 6aa76b1d - trellis, versa_ecp5: optional '-nowidelut' flag for yosys synth_ecp5 <Gabriel L. Somlo>
    * |   c954ff0c - Merge pull request #272 from sergachev/fix-comments <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 2f7bd971 - fix comments <Ilia Sergachev>
    * | ab4a5d1d - litex_setup: add litejesd204b <Florent Kermarrec>
    |/
    *   960b25a5 - Merge pull request #270 from gsomlo/gls-csr-upper <enjoy-digital>
    |\
    | * c8790d34 - soc/integration: ensure CSR constants are in uppercase <Gabriel Somlo>
    * | 41ad08e8 - soc/cores/icap: simplify ICAPBitstream (untested) <Florent Kermarrec>
    * | 0c299386 - soc/cores/icap: rename ICAP to ICAPBistream and revert old ICAP <Florent Kermarrec>
    * |   4bb2827e - Merge pull request #269 from antmicro/rework_icap <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 4423a46b - soc: cores: support sending custom bitstream to ICAP <Jan Kowalewski>
    * | 427d7af7 - soc/interconnect: rename stream_packet to packet & cleanup (with retro-compat) <Florent Kermarrec>
    * | 59bf04d9 - soc/interconnect/stream: add separators, mode Actor modules just after Endpoint <Florent Kermarrec>
    * | 59995c53 - soc_zynq: update get_csr_header <Florent Kermarrec>
    * | 4d90058b - soc/integration: move cpu_interface retro-compatibility to litex/__init__ <Florent Kermarrec>
    * | 8be5824e - soc/integration: use dicts for constants/mem_regions/csr_regions to cleanup/simplify iterations on theses <Florent Kermarrec>
    * | 7b72148c - cpu: remove initial SERV support (we'll work in a branch to experiment with it) <Florent Kermarrec>
    * | 63a813af - soc_core: fix cpu_type=None case and add test for it <Florent Kermarrec>
    * | 3d257d72 - soc_sdram: remove axi usecase, this was only useful to do some preliminary axi tests. <Florent Kermarrec>
    * | e8e57b4f - soc_core: cleanup/re-align <Florent Kermarrec>
    * | 334ae336 - soc/integration: rename cpu_interface to export (with retro-compat), re-arrange a bit, add separators <Florent Kermarrec>
    * | 241c3c64 - test/test_targets: update cpu-type to mor1kx <Florent Kermarrec>
    * | 48e5a1d1 - soc/cores: uniformize (continue) <Florent Kermarrec>
    * | e9ed4761 - soc/cores/gpio: uniformize with others cores <Florent Kermarrec>
    * | 78cecbe3 - soc/cores: rename frequency_meter to freqmeter and uniformize with others cores <Florent Kermarrec>
    * | 7575ecc6 - soc/cores/ecc: improve readibility, uniformize with others cores <Florent Kermarrec>
    * | c6fe3f31 - soc/cores/clocks: improve readibility <Florent Kermarrec>
    * | 6fcb12a9 - soc_core: use cpu.data_width to compute csr_alignment (and remove Rocket workaround) <Florent Kermarrec>
    * | b826c170 - soc/cores/cpus: improve ident/align, uniformize between cpus <Florent Kermarrec>
    * | 355072c2 - soc/cores/cpu: add CPU class and make all CPU inheritate from it <Florent Kermarrec>
    * | 2c3ad3f9 - soc_sdram: move ControllerInjector to LiteDRAM (LiteDRAMCore) <Florent Kermarrec>
    * | 101f1b1c - soc/integration: add common.py and move helpers from soc_core to it <Florent Kermarrec>
    * | 68ba1c60 - soc_core: avoid manual listing of support CPUs, just use CPU.keys() <Florent Kermarrec>
    * | 9095b80e - soc_core: remove add_cpu_or_bridge retro-compatibility (most of the designs have been updated since the change) <Florent Kermarrec>
    * | 8dd2dc1c - integration/soc_core: remove csr_map_update (no longer used) <Florent Kermarrec>
    * | da91aa43 - soc_core/cpu: move memory map override to CPUs, select reset_address after eventual memory map has override been done <Florent Kermarrec>
    * | 8099b0be - soc/cores/cpu: add set_reset_address method and use it instead of passing reset_address as a parameter <Florent Kermarrec>
    * | 7660dc22 - soc/cores/cpu: do instance in do_finalize for all cpus (allow updating parameters until the design is generated) <Florent Kermarrec>
    * | a3816096 - cores/cpu: define CPUS and simplify instance <Florent Kermarrec>
    * | 9f6a2ae7 - soc_core/serv: use UART_POLLING (no interrupt support) <Florent Kermarrec>
    * | a4069fc8 - add SERV submodule <Florent Kermarrec>
    * | 49594ed7 - software/libbase/uart: add polling mode <Florent Kermarrec>
    * | 3f95b9c0 - add SERV CPU initial support (not working) <Florent Kermarrec>
    * | 015b65fe - targets/ulx3s: revert to cl=2 <Florent Kermarrec>
    * | a9d55b04 - boards/netv2: switch to MVP, add spiflashx4 and hdmi in/out <Florent Kermarrec>
    * | 1425a68d - wishbone2csr: refactor using FSM, reduce latency (make it asynchronous) and set csr.adr only when access is done (allow use of CSR/CSRBase we signal) <Florent Kermarrec>
    * | ffd2be2b - csr: add we signal to CSR, CSRStatus <Florent Kermarrec>
    * | 47dc3324 - build/xilinx/programmer: fix vivado_cmd <Florent Kermarrec>
    * | ed9bff2e - soc/integration/doc: replace "== None" by "is None" <Florent Kermarrec>
    * |   836d5b88 - Merge pull request #266 from xobs/add-moduledoc-autodoc <enjoy-digital>
    |\ \
    | * | 68cea8c3 - timer: inherit ModuleDoc <Sean Cross>
    | * | 13197198 - integration: add ModuleDoc and AutoDoc <Sean Cross>
    * | | 78fb0fb9 - tools/litex_read_verilog: also delete yosys_v2j.ys <Florent Kermarrec>
    * | | 0ea7a1fd - soc_core/sdram: Don't blow up if _wb_sdram_ifs or _csr_masters are empty <Benjamin Herrenschmidt>
    * | |   742da31b - Merge pull request #264 from antmicro/mor1kx_linux <enjoy-digital>
    |\ \ \
    | * | | 5844376d - soc_core: adapt memory map for mainline Linux with mor1kx <Filip Kokosinski>
    | * | | 201218b2 - boards/targets: increase integrated ROM size if EthernetSoC is used <Filip Kokosinski>
    * | | | 06d08064 - soc_core: set csr to 0x00000000 when there is no wishbone <Florent Kermarrec>
    * | | | ad8830d9 - soc_sdram: Don't add the L2 Cache when there's no wishbone bus <Florent Kermarrec>
    |/ / /
    * | | ae38fd42 - soc_core: revert wishbone2csr to __init__ but add with_wishbone parameter <Florent Kermarrec>
    * | | 8c979565 - soc_sdram: change l2_size checks order <Florent Kermarrec>
    * | | a9acab99 - soc_core: move CSR bridge to finalize (only generate it if there is a wishbone master), revert default parameter when cpu_type is None (we have systems with cpu_type=None but that are using these peripherals) <Florent Kermarrec>
    * | | dde6dd02 - integration/builder: avoid specific _generate_standalone_includes <Florent Kermarrec>
    * | | 735ea196 - This will allow it to be built for microwatt out of tree <Benjamin Herrenschmidt>
    * | | c28086cd - soc_core: When cpu_type is "None", let's not generate useless UART, timer, ROMs, wishbone to CSR bridge etc... <Benjamin Herrenschmidt>
    * | | f909e4d7 - integration/builder: When the CPU is "None", we used to not generate any code. <Benjamin Herrenschmidt>
    |/ /
    * |   8b7d8217 - Merge pull request #263 from xobs/spi-flash-csrfield <enjoy-digital>
    |\ \
    | * | 1a6dddd5 - spi_flash: document register fields <Sean Cross>
    |/ /
    * |   4f659ba4 - Merge pull request #262 from jersey99/master <enjoy-digital>
    |\ \
    | * | 9ea11cf5 - vivado just needs to be in the path for the programmer as well <Vamsi K Vytla>
    |/ /
    * |   430fee4d - Merge pull request #261 from xobs/event-documentation <enjoy-digital>
    |\ \
    | |/
    |/|
    | * 60d8572c - csr_eventmanager: add `name` and `description` args <Sean Cross>
    |/
    * e2c78572 - cores/timer: add general documentation on Timer implementation and behavior. <Florent Kermarrec>
    * e97c1e36 - soc_sdram: improve readibility and convert l2_size to minimal allowed if provided l2_size is lower <Florent Kermarrec>
    * 99ed0877 - csr: add description to CSRStorage/CSRStatus attributes (thanks xobs) <Florent Kermarrec>
    * f2e84a58 - soc/cores/timer: fix typo (thanks xobs) <Florent Kermarrec>
    * 28885064 - soc/cores/timer/doc: rewrite a little bit, avoid some redundancy, change ident. <Florent Kermarrec>
    *   f1139c36 - Merge pull request #259 from xobs/document-timer <enjoy-digital>
    |\
    | * cb7d941a - timer: add documentation <Sean Cross>
    |/
    * cca0478a - soc/cores/spi: use new CSRField (no functional change) <Florent Kermarrec>
    * 80b2bef3 - soc/cores/bitbang: use new CSRField (no functional change) <Florent Kermarrec>
    *   3dc8d294 - Merge pull request #257 from enjoy-digital/csr_fields <enjoy-digital>
    |\
    | * 9bda614a - csr: update copyrights <Florent Kermarrec>
    | * 29134cc6 - csr: more documentation <Florent Kermarrec>
    | * 74e756aa - csr/CSRStorage: remove storage_full (was only needed by alignment_bits) <Florent Kermarrec>
    | * 5dc440e8 - csr: use IntEnum for CSRAccess <Florent Kermarrec>
    | * d2646f13 - csr/CSRStorage: remove alignment_bits: complexify too much code for the few use-cases it's really useful <Florent Kermarrec>
    | * 8e14694e - csr/fields: document, add separators, 100 characters per line <Florent Kermarrec>
    | * 4e84729c - csr/fields: add access parameter <Florent Kermarrec>
    | * 23b01f8f - csr/fields: add pulse mode support <Florent Kermarrec>
    | * 8c080e5f - soc/interconnect/csr: add initial field support <Florent Kermarrec>
    |/
    * c120f6d4 - build/openocd: add set_qe parameter to flash <Florent Kermarrec>
    * 6a0a1c9d - tools/litex_term/upload: bufferize only chunks of the file instead of the entire file to speedup upload when used on embedded devices (RPI for example) <Florent Kermarrec>
    * 16b6b357 - soc/integration/cpu_interface: don't raise OSError if we are not going to compile software and compilation toolchain is not found <Florent Kermarrec>
    * 62f53d50 - soc/integration/builder: call do_exit with vns when build is done. <Florent Kermarrec>
    *   cb5f1467 - Merge branch 'master' of http://github.com/enjoy-digital/litex <Florent Kermarrec>
    |\
    | *   a7b5c185 - Merge pull request #255 from sergachev/fix-crc32 <enjoy-digital>
    | |\
    | | * 2400f0f4 - fix crc32 <Ilia Sergachev>
    | |/
    * | 004c96b5 - soc/itnegration: update litedram <Florent Kermarrec>
    |/
    * 19f58dd9 - interconnect/wishbone: add FlipFlop to allow UpConverter to be used <Florent Kermarrec>
    * bd6ec63b - build/openocd: add stream method for JTAG UART <Florent Kermarrec>
    * b356204f - soc_core: add JTAG UART support (uart_name="jtag_uart) <Florent Kermarrec>
    * d0ebbda4 - soc/cores/jtag: add Xilinx JTAG TAPs support and simple JTAG PHY (can be used for JTAG UART) <Florent Kermarrec>
    * 2638393b - soc_zynq: fix indent <Florent Kermarrec>
    * 9051cf97 - soc_zynq: fix typo <Florent Kermarrec>
    * 67a09aef - soc/interconnect/stream: add Monitor module <Florent Kermarrec>
    *   6f150a56 - Merge pull request #254 from mithro/crc-smaller <enjoy-digital>
    |\
    | * 2a41f0d2 - Use `SMALL_CRC` to enable smaller CRC versions. <Tim 'mithro' Ansell>
    | * 08333744 - Remove extra whitespace. <Tim 'mithro' Ansell>
    | * c0e72386 - libbase: crc16: commit smaller version of crc16 <Sean Cross>
    | * a59d0efc - libbase: crc32: add smaller version <Sean Cross>
    * |   27c334d4 - Merge pull request #252 from mithro/only-change-on-contents <Tim Ansell>
    |\ \
    | |/
    |/|
    | * 3ff6a18a - Only write file if contents will change. <Tim 'mithro' Ansell>
    |/
    * a2938a7a - soc/cores: simplify JTAGAtlantic (only keep alt_jtag_atlantic instance), move to jtag and allow selecting it as uart with uart_name"jtag_atlantic" <Florent Kermarrec>
    *   19d3acfc - Merge pull request #251 from micro-FPGA/master <enjoy-digital>
    |\
    | * fb00ee85 - Create atlantic.py <Antti Lukats>
    | *   92e5b4b2 - Merge pull request #2 from enjoy-digital/master <Antti Lukats>
    | |\
    | * | f47e4978 - libero enable enhanced constraints <Antti Lukats>
    * | | 41fe7cae - core/spi: add minimal SPISlave <Florent Kermarrec>
    * | | b8457559 - gen/fhdl/verilog: allow single element verilog inline attribute <Florent Kermarrec>
    * | | 5a7b4c34 - targets/nexys_video: generate clk100 <Florent Kermarrec>
    * | | c179741c - software/bios: switch to standard CRLF <Florent Kermarrec>
    * | | 0328ba7d - tools/litex_term: add automatic check to see if we need to insert LF or not <Florent Kermarrec>
    * | | ffebd207 - bios/tools: allow disabling CRC check on serialboot (to speedup debug/loading large images when only serial is available) <Florent Kermarrec>
    * | | 4842bdcf - tools/litex_term: add sdl_payload_length <Florent Kermarrec>
    * | | 3e30c648 - litex_setup: add litex-boards <Florent Kermarrec>
    * | |   d79cd87d - Merge pull request #246 from gsomlo/gls-native-rv64 <enjoy-digital>
    |\ \ \
    | * | | 6d844a03 - software: use native toolchain for same host, target architectures <Gabriel L. Somlo>
    |/ / /
    * | |   d36f1fb7 - Merge pull request #244 from atommann/master <enjoy-digital>
    |\ \ \
    | |_|/
    |/| |
    | * | a45dbee5 - changing http to https <atommann>
    | * | 1d957d7a - Update .gitmodules <atommann>
    * | | 4990bf33 - soc/core: simplify/cleanup HyperRAM core - rename core to hyperbus. - change layout (cs_n with variable length instead of cs0_n, cs1_n). - use DifferentialOutput when differential clock is used. - add test (python3 -m unittest test.test_hyperbus). <Florent Kermarrec>
    * | | d1502d41 - soc/cores: add initial simple hyperram core <Antti Lukats>
    | |/
    |/|
    * | 6e6fe83a - build/altera/quartus: add add_ip method to use Quartus QSYS files <Florent Kermarrec>
    * | 2899928a - cpu_interface: add json csr map export, simplify csv csr map export using json <Florent Kermarrec>
    * | 9d4b7cd5 - bios/sdram: set init done after memtest (for standalone LiteDRAM controllers) <Florent Kermarrec>
    * | 0cd4e45f - build/xilinx/vivado: use "" for strings <Florent Kermarrec>
    * | 8d161a47 - build/xilinx/vivado: remove with_phys_opt <Florent Kermarrec>
    * |   f6638ded - Merge pull request #243 from sergachev/master <enjoy-digital>
    |\ \
    | * | 861eea8a - build/xilinx/vivado: improve directive support <Ilia Sergachev>
    * | |   ccc2cbd9 - Merge pull request #241 from railnova/zynq <enjoy-digital>
    |\ \ \
    | |/ /
    |/| |
    | * | db4c609a - [fix] prevent Vivado from inferring DSP48 in AXIBurst2Beat <chmousset>
    |/ /
    * | 6d5fddc1 - cores/spi_flash/S7SPIFlash: make cs_n optional in pads (when driven externally) <Florent Kermarrec>
    * |   383c05e2 - Merge pull request #240 from danielkucera/patch-1 <enjoy-digital>
    |\ \
    | |/
    |/|
    | * a5eaf172 - more understandable error when missing a memory <Daniel Kucera>
    |/
    *   2b815f70 - Merge pull request #235 from gsomlo/gls-trellis-yosys-opt <enjoy-digital>
    |\
    | * 6c298cb7 - build/lattice/trellis: use abc9 techmapping pass with yosys <Gabriel L. Somlo>
    |/
    * 31bfb546 - software/libbase/mdio: set data before clock, revert two cycle turnaround and test with different phys <Florent Kermarrec>
    * e670cb91 - cores/cpu: add riscv-none-embed toolchain support to riscv32 cpus <Florent Kermarrec>
    * 6d94c07d - software/libase/mdio: cleanup and reduce raw_turnaround by 1 cycle <Florent Kermarrec>
    * 0c287b11 - cores/clock/S7PLL: fix -1/-3 speedgrade vco max freq swap <Florent Kermarrec>
    * 82cd557c - software/bios: add Ethernet PHY MDIO read/write/dump commands <Florent Kermarrec>
    * 0ba9ab92 - altera/common: fix AsyncResetSynchronizer polarity and simplify <Florent Kermarrec>
    * 124dff8f - build/xilinx/common: improve presentation <Florent Kermarrec>
    * 60873a5b - microsemi/common: improve presentation <Florent Kermarrec>
    * 36d9d78c - build/altera/common: improve presentation <Florent Kermarrec>
    * 95953d29 - platforms/default_clk_period: use 1e9/freq <Florent Kermarrec>
    * f1d8c70b - targets/minispartan6/crg: only keep S6PLL code <Florent Kermarrec>
    * d3d0a623 - cores/clock: juse use 1e9/freq instead of period_ns <Florent Kermarrec>
    * a881817f - cores/clock/s6pll: add phase support <Florent Kermarrec>
    * 6b7ca0cf - cores/clock/xilinx: change clkfbout_mult loop order to select highest vco_freq <Florent Kermarrec>
    * 1884649d - litex_term: make sure to unconfigure console when board is unplugged <Florent Kermarrec>
    * e052d7f6 - soc/integration/builder: -x <Florent Kermarrec>
    * 236070fd - cores: -x on spi.py <Florent Kermarrec>
    * a9fe2788 - wishbone/SRAM: make read_only emited verilog code compatible with all tools <Florent Kermarrec>
    * ce5c5859 - soc/cores/uart: add FT245 FIFO mode support (sync & async) <Florent Kermarrec>
    * a496760c - build/altera/quartus: use .bat on win32/cygwin <Florent Kermarrec>
    * 7e0ea070 - build/xilinx/vivado: change severity of Common 17-55 critical warning to warning <Florent Kermarrec>
    * 92d93ad2 - cores/pwm: remove default CSR reset values. <Florent Kermarrec>
    * 25ca0a8b - soc: generate git header and show migen/litex git sha1 in bios <Florent Kermarrec>
    * ae00482d - Merge pull request #223 from sergachev/master <enjoy-digital>
    * fdb119cb - support vivado incremental implementation <Ilia Sergachev>

 * litex-renode changed from b3fdb9b to 742360f
    *   742360f - Merge pull request #15 from antmicro/zephyr_dts <Tim Ansell>
    |\
    | * c9b9651 - Add script generating DTS overlay for Zephyr <Mateusz Holenko>
    * | b0ebee5 - Merge pull request #14 from antmicro/memory_regions_verification <Mateusz Hołenko>
    |/
    * ad52a03 - Verify memory sub-regions <Mateusz Holenko>
    * 2cb6886 - Rework handling address/size values in `Configuration` <Mateusz Holenko>
    * 462df23 - Simplify flash memory generation <Mateusz Holenko>
    * 3a1f7c8 - Generate memory regions size in hex <Mateusz Holenko>
    * f010339 - Print peripheral address in hex <Mateusz Holenko>
    * 0742996 - Fix a typo <Mateusz Holenko>

 * migen changed from 0.6.dev-289-g5585912 to 0.6.dev-306-g41922fd
    * 41922fd - sayma_amc2: amc_fpga_sysref* <Sebastien Bourdeauducq>
    * 3714470 - sayma_amc: fix dac_sync pin locations <Sebastien Bourdeauducq>
    * 4a6ef29 - sayma_amc2: DAC JESD links have been swapped <Sebastien Bourdeauducq>
    * 3012df6 - sayma_amc2: sma_io -> mcx_io <Sebastien Bourdeauducq>
    * ecf8412 - sayma2: remove serwb <Sebastien Bourdeauducq>
    * fc31a9e - sayma_rtm2: add HMC workaround signals <Sebastien Bourdeauducq>
    * 21b2fbd - sayma_rtm2: fix swapped scl/sda <Sebastien Bourdeauducq>
    * 0114468 - sayma_rtm2: cross UART <Sebastien Bourdeauducq>
    * 5a28590 - sayma_rtm2: clk50 is DNP, use GTP clock instead <Sebastien Bourdeauducq>
    * ef7dab2 - sayma_rtm2: always xc7a50t <Sebastien Bourdeauducq>
    * 63a5f55 - sayma_rtm2: add filtered_clk_sel signal <Sebastien Bourdeauducq>
    * 9211304 - sayma_amc2: add filtered_clk_sel signal <Sebastien Bourdeauducq>
    * 9e59e41 - sayma_amc2: fix typo in previous commit <Sebastien Bourdeauducq>
    * 58d9c82 - sayma_amc2: fix ddram_32 assignments <Sebastien Bourdeauducq>
    * 57a7311 - Added support for the Xilinx AC701 FPGA development board <Tobias Rosenkranz>
    * f4fcd10 - fix previous commit <Sebastien Bourdeauducq>
    * 34f24f3 - zedboard: use Vivado toolchain <Sebastien Bourdeauducq>

Full submodule status
--
 3a6108a75be356a3dc53760d22782f1323248b6b edid-decode (remotes/origin/HEAD)
 01d8f819f15baf9a8cc5d96945a51e4d267ff564 flash_proxies (remotes/origin/HEAD)
 401554f94c5fbfae1a4de98504c5c2994a6f714a litedram (remotes/origin/HEAD)
 4d9e74f10a3fe7bf71ba9bde50f49689c6458dc5 liteeth (remotes/origin/HEAD)
 47e76f447f6e3d97aac2638a98f967d44db5c349 litepcie (remotes/origin/HEAD)
 db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 litesata (remotes/origin/HEAD)
 7a9fa9d3b18362bf707dff25a78661395ef9ee7a litescope (remotes/origin/HEAD)
 7457a29b1a47fe15e81fa37f3bbdd510788f1d53 liteusb (remotes/origin/HEAD)
 49bafa481075e0bfbaf067b63c351ec29e993894 litevideo (remotes/origin/HEAD)
 a54b80b9b4eaa6defca99b0749da8426535bbb62 litex (v0.1-1333-ga54b80b9)
 742360f2ba4c400c6164908f03c6ca3d965f168b litex-renode (remotes/origin/HEAD)
 41922fde2a8c36cd0f99d4b7ebb3ba9c37ce1489 migen (0.6.dev-306-g41922fd)
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Reviewers
No reviews
Assignees
No one assigned
Labels
boards-all firmware-cypress-fx2 firmware-fpga firmware-softcpu hdmi2*** type-enhancement
Projects
None yet
Milestone
No milestone
Development

Successfully merging this pull request may close these issues.

None yet
3 participants
@sealne @landscape-bot @mithro