sayma_rtm: attenuator reset is active-low

sbourdeauducq · sbourdeauducq · commit e97f8dbe785c · 2017-12-15T13:08:01.000+08:00
diff --git a/migen/build/platforms/sinara/sayma_rtm.py b/migen/build/platforms/sinara/sayma_rtm.py
@@ -70,56 +70,56 @@
         Subsignal("le", Pins("U2")),
         Subsignal("sin", Pins("T4")),
         Subsignal("clk", Pins("V3")),
-        Subsignal("rst", Pins("R3")),
+        Subsignal("rst_n", Pins("R3")),
         IOStandard("LVCMOS25")
     ),
     ("allaki0_att1", 1,
         Subsignal("le", Pins("P1")),
         Subsignal("sin", Pins("P3")),
         Subsignal("clk", Pins("N3")),
-        Subsignal("rst", Pins("M4")),
+        Subsignal("rst_n", Pins("M4")),
         IOStandard("LVCMOS25")
     ),
     ("allaki1_att0", 1,
         Subsignal("le", Pins("U7")),
         Subsignal("sin", Pins("R6")),
         Subsignal("clk", Pins("V8")),
-        Subsignal("rst", Pins("R7")),
+        Subsignal("rst_n", Pins("R7")),
         IOStandard("LVCMOS25")
     ),
     ("allaki1_att1", 1,
         Subsignal("le", Pins("T3")),
         Subsignal("sin", Pins("U5")),
         Subsignal("clk", Pins("P6")),
-        Subsignal("rst", Pins("U4")),
+        Subsignal("rst_n", Pins("U4")),
         IOStandard("LVCMOS25")
     ),
     ("allaki2_att0", 1,
         Subsignal("le", Pins("C13")),
         Subsignal("sin", Pins("E16")),
         Subsignal("clk", Pins("D14")),
-        Subsignal("rst", Pins("A15")),
+        Subsignal("rst_n", Pins("A15")),
         IOStandard("LVCMOS25")
     ),
     ("allaki2_att1", 1,
         Subsignal("le", Pins("D11")),
         Subsignal("sin", Pins("C14")),
         Subsignal("clk", Pins("A12")),
-        Subsignal("rst", Pins("C12")),
+        Subsignal("rst_n", Pins("C12")),
         IOStandard("LVCMOS25")
     ),
     ("allaki3_att0", 1,
         Subsignal("le", Pins("M2")),
         Subsignal("sin", Pins("N1")),
         Subsignal("clk", Pins("M6")),
-        Subsignal("rst", Pins("L5")),
+        Subsignal("rst_n", Pins("L5")),
         IOStandard("LVCMOS25")
     ),
     ("allaki3_att1", 1,
         Subsignal("le", Pins("K5")),
         Subsignal("sin", Pins("L2")),
         Subsignal("clk", Pins("K2")),
-        Subsignal("rst", Pins("J5")),
+        Subsignal("rst_n", Pins("J5")),
         IOStandard("LVCMOS25")
     ),
 ]
