Skip to content

Commit 8e87a14

Browse files
sbourdeauducqsbourdeauducq
committedDec 14, 2017
sayma_rtm: add Allaki control pins
1 parent 271d7f0 commit 8e87a14

File tree

1 file changed

+67
-0
lines changed

1 file changed

+67
-0
lines changed
 

Diff for: ‎migen/build/platforms/sinara/sayma_rtm.py

+67
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,73 @@
5555
IOStandard("LVCMOS25")
5656
),
5757
("ad9154_txen", 1, Pins("L17 L14"), IOStandard("LVCMOS25")),
58+
59+
# Allaki
60+
("allaki0_rfsw0", 1, Pins("R2"), IOStandard("LVCMOS25")),
61+
("allaki0_rfsw1", 1, Pins("N4"), IOStandard("LVCMOS25")),
62+
("allaki1_rfsw0", 1, Pins("R5"), IOStandard("LVCMOS25")),
63+
("allaki1_rfsw1", 1, Pins("V4"), IOStandard("LVCMOS25")),
64+
("allaki2_rfsw0", 1, Pins("B15"), IOStandard("LVCMOS25")),
65+
("allaki2_rfsw1", 1, Pins("B12"), IOStandard("LVCMOS25")),
66+
("allaki3_rfsw0", 1, Pins("L4"), IOStandard("LVCMOS25")),
67+
("allaki3_rfsw1", 1, Pins("J4"), IOStandard("LVCMOS25")),
68+
69+
("allaki0_att0", 1,
70+
Subsignal("le", Pins("U2")),
71+
Subsignal("sin", Pins("T4")),
72+
Subsignal("clk", Pins("V3")),
73+
Subsignal("rst", Pins("R3")),
74+
IOStandard("LVCMOS25")
75+
),
76+
("allaki0_att1", 1,
77+
Subsignal("le", Pins("P1")),
78+
Subsignal("sin", Pins("P3")),
79+
Subsignal("clk", Pins("N3")),
80+
Subsignal("rst", Pins("M4")),
81+
IOStandard("LVCMOS25")
82+
),
83+
("allaki1_att0", 1,
84+
Subsignal("le", Pins("U7")),
85+
Subsignal("sin", Pins("R6")),
86+
Subsignal("clk", Pins("V8")),
87+
Subsignal("rst", Pins("R7")),
88+
IOStandard("LVCMOS25")
89+
),
90+
("allaki1_att1", 1,
91+
Subsignal("le", Pins("T3")),
92+
Subsignal("sin", Pins("U5")),
93+
Subsignal("clk", Pins("P6")),
94+
Subsignal("rst", Pins("U4")),
95+
IOStandard("LVCMOS25")
96+
),
97+
("allaki2_att0", 1,
98+
Subsignal("le", Pins("C13")),
99+
Subsignal("sin", Pins("E16")),
100+
Subsignal("clk", Pins("D14")),
101+
Subsignal("rst", Pins("A15")),
102+
IOStandard("LVCMOS25")
103+
),
104+
("allaki2_att1", 1,
105+
Subsignal("le", Pins("D11")),
106+
Subsignal("sin", Pins("C14")),
107+
Subsignal("clk", Pins("A12")),
108+
Subsignal("rst", Pins("C12")),
109+
IOStandard("LVCMOS25")
110+
),
111+
("allaki3_att0", 1,
112+
Subsignal("le", Pins("M2")),
113+
Subsignal("sin", Pins("N1")),
114+
Subsignal("clk", Pins("M6")),
115+
Subsignal("rst", Pins("L5")),
116+
IOStandard("LVCMOS25")
117+
),
118+
("allaki3_att1", 1,
119+
Subsignal("le", Pins("K5")),
120+
Subsignal("sin", Pins("L2")),
121+
Subsignal("clk", Pins("K2")),
122+
Subsignal("rst", Pins("J5")),
123+
IOStandard("LVCMOS25")
124+
),
58125
]
59126

60127

0 commit comments

Comments
 (0)
Please sign in to comment.