timvideos · Dec 3, 2017 · Dec 3, 2017 · Dec 3, 2017 · Dec 3, 2017 · Dec 3, 2017
diff --git a/.travis.yml b/.travis.yml
@@ -25,6 +25,9 @@ env:
   global:
    - HDMI2USB_UDEV_IGNORE=1
    - CLEAN_CHECK=1
+   # Travis reports incorrect the hosts number of processors, override to 2
+   # cores.
+   - JOBS=2
 
 install:
  - export CPU="$C"

diff --git a/Makefile b/Makefile
@@ -35,6 +35,13 @@ FIRMWARE ?= firmware
 CLANG = 0
 export CLANG
 
+JOBS ?= $(shell nproc)
+JOBS ?= 2
+
+ifeq ($(shell [ $(JOBS) -gt 1 ] && echo true),true)
+    export MAKEFLAGS="-j $(JOBS) -l $(JOBS)"
+endif
+
 ifeq ($(PLATFORM_EXPANSION),)
 FULL_PLATFORM = $(PLATFORM)
 else
@@ -82,7 +89,6 @@ build/cache.mk: targets/*/*.py scripts/makefile-cache.sh
 
 TARGETS=$(TARGETS_$(PLATFORM))
 
-
 # Initialize submodules automatically
 third_party/%/.git: .gitmodules
 	git submodule sync --recursive -- $$(dirname $@)
@@ -121,6 +127,7 @@ image-flash-py: image
 	$(PYTHON) flash.py --mode=image
 
 .PHONY: image image-load image-flash image-flash-py image-flash-$(PLATFORM) image-load-$(PLATFORM)
+.NOTPARALLEL: image-load image-flash image-flash-py image-flash-$(PLATFORM) image-load-$(PLATFORM)
 
 # Gateware - the stuff which configures the FPGA.
 # --------------------------------------
@@ -160,6 +167,7 @@ gateware-clean:
 	rm -rf $(TARGET_BUILD_DIR)/gateware
 
 .PHONY: gateware gateware-load gateware-flash gateware-flash-py gateware-clean gateware-load-$(PLATFORM) gateware-flash-$(PLATFORM)
+.NOTPARALLEL: gateware-load gateware-flash gateware-flash-py gateware-flash-$(PLATFORM) gateware-load-$(PLATFORM)
 
 # Firmware - the stuff which runs in the soft CPU inside the FPGA.
 # --------------------------------------
@@ -196,15 +204,16 @@ firmware-connect: firmware-connect-$(PLATFORM)
 firmware-clear: firmware-clear-$(PLATFORM)
 	@true
 
-.PHONY: firmware-load-$(PLATFORM) firmware-flash-$(PLATFORM) firmware-connect-$(PLATFORM) firmware-clear-$(PLATFORM)
-
 firmware-clean:
 	rm -rf $(TARGET_BUILD_DIR)/software
 
 firmware-test:
-	firmware/test.sh
+	scripts/check-firmware-newlines.sh
 
+.PHONY: firmware-load-$(PLATFORM) firmware-flash-$(PLATFORM) firmware-flash-py firmware-connect-$(PLATFORM) firmware-clear-$(PLATFORM)
+.NOTPARALLEL: firmware-load-$(PLATFORM) firmware-flash-$(PLATFORM) firmware-flash-py firmware-connect-$(PLATFORM) firmware-clear-$(PLATFORM)
 .PHONY: firmware-cmd $(FIRMWARE_FILEBASE).bin firmware firmware-load firmware-flash firmware-connect firmware-clean firmware-test
+.NOTPARALLEL: firmware-cmd firmware-load firmware-flash firmware-connect
 
 $(BIOS_FILE): firmware-cmd
 	@true
@@ -216,6 +225,7 @@ bios-flash: $(BIOS_FILE) bios-flash-$(PLATFORM)
 	@true
 
 .PHONY: $(FIRMWARE_FILE) bios bios-flash bios-flash-$(PLATFORM)
+.NOTPARALLEL: bios-flash bios-flash-$(PLATFORM)
 
 
 # TFTP booting stuff
@@ -244,6 +254,7 @@ tftpd_start:
 	fi
 
 .PHONY: tftp tftpd_stop tftpd_start
+.NOTPARALLEL: tftp tftpd_stop tftpd_start
 
 # Extra targets
 # --------------------------------------
@@ -267,6 +278,7 @@ env:
 	@# Hardcoded values
 	@echo "export CLANG=$(CLANG)"
 	@echo "export PYTHONHASHSEED=$(PYTHONHASHSEED)"
+	@echo "export JOBS=$(JOBS)"
 	@# Files
 	@echo "export IMAGE_FILE='$(IMAGE_FILE)'"
 	@echo "export GATEWARE_FILEBASE='$(GATEWARE_FILEBASE)'"
@@ -364,7 +376,8 @@ clean:
 dist-clean:
 	rm -rf build
 
-.PHONY: flash help clean dist-clean help-$(PLATFORM) reset reset-$(PLATFORM)
+.PHONY: flash env info prompt help clean dist-clean help-$(PLATFORM) reset reset-$(PLATFORM)
+.NOTPARALLEL: flash env prompt info help help-$(PLATFORM) reset reset-$(PLATFORM)
 
 # Tests
 # --------------------------------------
@@ -379,3 +392,4 @@ test: firmware-test
 	@echo "Tests passed"
 
 .PHONY: test test-edid
+.NOTPARALLEL: test test-edid
diff --git a/firmware/ci.c b/firmware/ci.c
@@ -940,7 +940,7 @@ static void debug_clocks(void)
 {
 	// Only the active clock system will output anything
 	pll_dump();
-	mmcm_dump();
+	mmcm_dump_all();
 }
 
 static unsigned int log2(unsigned int v)

diff --git a/firmware/mmcm.c b/firmware/mmcm.c
@@ -8,92 +8,114 @@
  * Despite varying pixel clocks, we must keep the PLL VCO operating
  * in the specified range of 600MHz - 1200MHz.
  */
-#ifdef CSR_HDMI_OUT0_CLOCKING_MMCM_RESET_ADDR
-void hdmi_out0_mmcm_write(int adr, int data) {
+#ifdef CSR_HDMI_OUT0_DRIVER_CLOCKING_MMCM_RESET_ADDR
+void hdmi_out0_driver_clocking_mmcm_write(int adr, int data)
+{
 	hdmi_out0_driver_clocking_mmcm_adr_write(adr);
 	hdmi_out0_driver_clocking_mmcm_dat_w_write(data);
 	hdmi_out0_driver_clocking_mmcm_write_write(1);
 	while(!hdmi_out0_driver_clocking_mmcm_drdy_read());
 }
 
-int hdmi_out0_mmcm_read(int adr) {
+int hdmi_out0_driver_clocking_mmcm_read(int adr)
+{
 	hdmi_out0_driver_clocking_mmcm_adr_write(adr);
 	hdmi_out0_driver_clocking_mmcm_read_write(1);
 	while(!hdmi_out0_driver_clocking_mmcm_drdy_read());
 	return hdmi_out0_driver_clocking_mmcm_dat_r_read();
 }
+
+MMCM hdmi_out0_driver_clocking_mmcm = {
+	.write = &hdmi_out0_driver_clocking_mmcm_write,
+	.read = &hdmi_out0_driver_clocking_mmcm_read,
+};
 #endif
 
 #ifdef CSR_HDMI_IN0_CLOCKING_MMCM_RESET_ADDR
-void hdmi_in0_clocking_mmcm_write(int adr, int data) {
+void hdmi_in0_clocking_mmcm_write(int adr, int data)
+{
 	hdmi_in0_clocking_mmcm_adr_write(adr);
 	hdmi_in0_clocking_mmcm_dat_w_write(data);
 	hdmi_in0_clocking_mmcm_write_write(1);
 	while(!hdmi_in0_clocking_mmcm_drdy_read());
 }
 
-int hdmi_in0_clocking_mmcm_read(int adr) {
+int hdmi_in0_clocking_mmcm_read(int adr)
+{
 	hdmi_in0_clocking_mmcm_adr_write(adr);
 	hdmi_in0_clocking_mmcm_read_write(1);
 	while(!hdmi_in0_clocking_mmcm_drdy_read());
 	return hdmi_in0_clocking_mmcm_dat_r_read();
 }
 
-static void hdmi_in_0_config_30_60mhz(void) {
-	hdmi_in0_clocking_mmcm_write(0x14, 0x1000 | (10<<6) | 10); /* clkfbout_mult  = 20 */
-	hdmi_in0_clocking_mmcm_write(0x08, 0x1000 | (10<<6) | 10); /* clkout0_divide = 20 */
-	hdmi_in0_clocking_mmcm_write(0x0a, 0x1000 |  (8<<6) |  8); /* clkout1_divide = 16 */
-	hdmi_in0_clocking_mmcm_write(0x0c, 0x1000 |  (2<<6) |  2); /* clkout2_divide =  4 */
-	hdmi_in0_clocking_mmcm_write(0x0d, 0);                     /* clkout2_divide =  4 */
+MMCM hdmi_in0_clocking_mmcm = {
+	.write = &hdmi_in0_clocking_mmcm_write,
+	.read = &hdmi_in0_clocking_mmcm_read,
+};
+#endif
+
+static void mmcm_config_30to60mhz(MMCM *mmcm)
+{
+	mmcm->write(0x14, 0x1000 | (10<<6) | 10); /* clkfbout_mult  = 20 */
+	mmcm->write(0x08, 0x1000 | (10<<6) | 10); /* clkout0_divide = 20 */
+	mmcm->write(0x0a, 0x1000 |  (8<<6) |  8); /* clkout1_divide = 16 */
+	mmcm->write(0x0c, 0x1000 |  (2<<6) |  2); /* clkout2_divide =  4 */
+	mmcm->write(0x0d, 0);                     /* clkout2_divide =  4 */
 }
 
-static void hdmi_in_0_config_60_120mhz(void) {
-	hdmi_in0_clocking_mmcm_write(0x14, 0x1000 |  (5<<6) | 5); /* clkfbout_mult  = 10 */
-	hdmi_in0_clocking_mmcm_write(0x08, 0x1000 |  (5<<6) | 5); /* clkout0_divide = 10 */
-	hdmi_in0_clocking_mmcm_write(0x0a, 0x1000 |  (4<<6) | 4); /* clkout1_divide =  8 */
-	hdmi_in0_clocking_mmcm_write(0x0c, 0x1000 |  (1<<6) | 1); /* clkout2_divide =  2 */
-	hdmi_in0_clocking_mmcm_write(0x0d, 0);                    /* clkout2_divide =  2 */
+static void mmcm_config_60to120mhz(MMCM *mmcm)
+{
+	mmcm->write(0x14, 0x1000 |  (5<<6) | 5); /* clkfbout_mult  = 10 */
+	mmcm->write(0x08, 0x1000 |  (5<<6) | 5); /* clkout0_divide = 10 */
+	mmcm->write(0x0a, 0x1000 |  (4<<6) | 4); /* clkout1_divide =  8 */
+	mmcm->write(0x0c, 0x1000 |  (1<<6) | 1); /* clkout2_divide =  2 */
+	mmcm->write(0x0d, 0);                    /* clkout2_divide =  2 */
 }
 
-static void hdmi_in_0_config_120_240mhz(void) {
-	hdmi_in0_clocking_mmcm_write(0x14, 0x1000 |  (2<<6) | 3);  /* clkfbout_mult  = 5 */
-	hdmi_in0_clocking_mmcm_write(0x08, 0x1000 |  (2<<6) | 3);  /* clkout0_divide = 5 */
-	hdmi_in0_clocking_mmcm_write(0x0a, 0x1000 |  (2<<6) | 2);  /* clkout1_divide = 4 */
-	hdmi_in0_clocking_mmcm_write(0x0c, 0x1000 |  (0<<6) | 0);  /* clkout2_divide = 1 */
-	hdmi_in0_clocking_mmcm_write(0x0d, (1<<6));                /* clkout2_divide = 1 */
+static void mmcm_config_120to240mhz(MMCM *mmcm)
+{
+	mmcm->write(0x14, 0x1000 |  (2<<6) | 3);  /* clkfbout_mult  = 5 */
+	mmcm->write(0x08, 0x1000 |  (2<<6) | 3);  /* clkout0_divide = 5 */
+	mmcm->write(0x0a, 0x1000 |  (2<<6) | 2);  /* clkout1_divide = 4 */
+	mmcm->write(0x0c, 0x1000 |  (0<<6) | 0);  /* clkout2_divide = 1 */
+	mmcm->write(0x0d, (1<<6));                /* clkout2_divide = 1 */
 }
 
-void mmcm_config_for_clock(int freq)
+void mmcm_config_for_clock(MMCM *mmcm, int freq)
 {
 	/*
 	 * FIXME: we also need to configure phase detector
 	 */
 	if(freq < 3000)
 		wprintf("Frequency too low for input MMCMs\n");
 	else if(freq < 6000)
-		hdmi_in_0_config_30_60mhz();
+		mmcm_config_30to60mhz(mmcm);
 	else if(freq < 12000)
-		hdmi_in_0_config_60_120mhz();
+		mmcm_config_60to120mhz(mmcm);
 	else if(freq < 24000)
-		hdmi_in_0_config_120_240mhz();
+		mmcm_config_120to240mhz(mmcm);
 	else
 		wprintf("Frequency too high for input MMCMs\n");
 }
-#endif
 
-void mmcm_dump(void)
+void mmcm_dump(MMCM* mmcm)
 {
 	int i;
-#ifdef CSR_HDMI_OUT0_CLOCKING_MMCM_RESET_ADDR
-	wprintf("framebuffer MMCM:\n");
 	for(i=0;i<128;i++)
-		wprintf("%04x ", hdmi_out0_mmcm_read(i));
-	wputchar("\n");
+		printf("%04x ", mmcm->read(i));
+
+}
+void mmcm_dump_all(void)
+{
+	int i;
+#ifdef CSR_HDMI_OUT0_DRIVER_CLOCKING_MMCM_RESET_ADDR
+	printf("framebuffer MMCM:\n");
+	mmcm_dump(&hdmi_out0_driver_clocking_mmcm);
+	printf("\n");
 #endif
 #ifdef CSR_HDMI_IN0_CLOCKING_MMCM_RESET_ADDR
-	wprintf("dvisampler MMCM:\n");
-	for(i=0;i<128;i++)
-		wprintf("%04x ", hdmi_in0_clocking_mmcm_read(i));
-	wputchar('\n');
+	printf("dvisampler MMCM:\n");
+	mmcm_dump(&hdmi_in0_clocking_mmcm);
+	printf("\n");
 #endif
 }
diff --git a/firmware/mmcm.h b/firmware/mmcm.h
@@ -3,16 +3,28 @@
 
 #include <generated/csr.h>
 
-#ifdef CSR_HDMI_IN0_CLOCKING_MMCM_RESET_ADDR
+typedef void (*mmcm_write_t)(int,int);
+typedef int (*mmcm_read_t)(int);
 
-void hdmi_out0_mmcm_write(int adr, int data);
-int hdmi_out0_mmcm_read(int adr);
-void hdmi_in0_clocking_mmcm_write(int adr, int data);
-int hdmi_in0_clocking_mmcm_read(int adr);
+typedef struct {
+	mmcm_write_t write;
+	mmcm_read_t  read;
+} MMCM;
+
+void mmcm_config_for_clock(MMCM *mmcm, int freq);
+void mmcm_dump(MMCM *mmcm);
+void mmcm_dump_all(void);
 
-void mmcm_config_for_clock(int freq);
+#ifdef CSR_HDMI_OUT0_DRIVER_CLOCKING_MMCM_RESET_ADDR
+void hdmi_out0_driver_clocking_mmcm_write(int adr, int data);
+int hdmi_out0_driver_clocking_mmcm_read(int adr);
+extern MMCM hdmi_out0_driver_clocking_mmcm;
 #endif
 
-void mmcm_dump(void);
+#ifdef CSR_HDMI_IN0_CLOCKING_MMCM_RESET_ADDR
+void hdmi_in0_clocking_mmcm_write(int adr, int data);
+int hdmi_in0_clocking_mmcm_read(int adr);
+extern MMCM hdmi_in0_clocking_mmcm;
+#endif
 
 #endif