saturn: adding platform and base target #381
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FelixVi
commented
Dec 9, 2017
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FelixVi
commented
| @@ -0,0 +1,148 @@ | |||
| from litex.build.generic_platform import * | |||
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Can you add an header line which mentions where this part comes from? See the example here -> https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/platforms/atlys.py#L1
targets/saturn/base.py
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| f = Fraction(50, 5) | ||
| n, d = f.numerator, f.denominator | ||
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| print("fvco (MHz) = {0}".format(f0*n/d/1000000)) |
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Can you remove the print statements?
targets/saturn/base.py
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| # PLL signals | ||
| pll_lckd = Signal() | ||
| pll_fb = Signal() |
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Can you wrap the PLL code like this -> https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/targets/atlys/base.py#L53-L100
targets/saturn/base.py
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| self.clk4x_wr_strb = Signal() | ||
| self.clk4x_rd_strb = Signal() | ||
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| # sdram_full |
targets/saturn/base.py
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| self.specials += Instance("BUFG", i_I=unbuf_sdram_half_a, o_O=self.cd_sdram_half.clk) | ||
| clk_sdram_half_shifted = Signal() | ||
| self.specials += Instance("BUFG", i_I=unbuf_sdram_half_b, o_O=clk_sdram_half_shifted) | ||
| clk = platform.request("ddram_clock") |
targets/saturn/base.py
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| mem_map = { | ||
| "spiflash": 0x20000000, # (default shadow @0xa0000000) | ||
| } | ||
| mem_map.update(SoCSDRAM.mem_map) |
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Can you leave the spiflash out for now?
targets/saturn/base.py
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| # sdram | ||
| sdram_module = MT46H32M16(self.clk_freq, "1:2") | ||
| self.submodules.ddrphy = s6ddrphy.S6HalfRateDDRPHY(platform.request("ddram"), |
targets/saturn/base.py
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| self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size | ||
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| SoC = BaseSoC | ||
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platforms/saturn.py
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| from litex.build.generic_platform import * | ||
| from litex.build.xilinx import XilinxPlatform | ||
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| #this is for the LX45 version |
platforms/saturn.py
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| IOStandard("LVTTL") | ||
| ), | ||
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| ("usb_fifo", 0, |
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What type of USB FIFO is on this board?
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It's the FT2232H - one channel for JTAG, the other as FIFO
Should there be a note in the platform file?
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Can you please add a description in your commit message? This string from platforms/saturn.py would be a good starting point:
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Support for the Numato Saturn (LX45 version)
(http://numato.com/product/saturn-spartan-6-fpga-development-board-with-ddr-sdram)
Board comes with DDR SDRAM, USB-FIFO and lots of GPIO on 100mil headers
max frequency can be further optimized
