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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: f3a2b3a67ed6
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 10, 2016

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    de718fc View commit details
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    f3a2b3a View commit details
Showing with 14 additions and 4 deletions.
  1. +2 −2 artiq/gateware/rtio/core.py
  2. +12 −2 artiq/test/coredevice/test_rtio.py
4 changes: 2 additions & 2 deletions artiq/gateware/rtio/core.py
Original file line number Diff line number Diff line change
@@ -158,8 +158,8 @@ def __init__(self, interface, counter, fifo_depth, guard_io_cycles):
self.sync.rsys += sequence_error.eq(self.ev.timestamp[fine_ts_width:] <
buf.timestamp[fine_ts_width:])
if interface.enable_replace:
if hasattr(self.ev, "a"):
different_addresses = self.ev.a != buf.a
if address_width:
different_addresses = self.ev.address != buf.address
else:
different_addresses = 0
if fine_ts_width:
14 changes: 12 additions & 2 deletions artiq/test/coredevice/test_rtio.py
Original file line number Diff line number Diff line change
@@ -12,6 +12,10 @@
artiq_low_latency = os.getenv("ARTIQ_LOW_LATENCY")


class PulseNotReceived(Exception):
pass


class RTT(EnvExperiment):
def build(self):
self.setattr_device("core")
@@ -29,7 +33,10 @@ def run(self):
delay(1*us)
t0 = now_mu()
self.ttl_inout.pulse(1*us)
self.set_dataset("rtt", mu_to_seconds(self.ttl_inout.timestamp_mu() - t0))
t1 = self.ttl_inout.timestamp_mu()
if t1 < 0:
raise PulseNotReceived()
self.set_dataset("rtt", mu_to_seconds(t1 - t0))


class Loopback(EnvExperiment):
@@ -48,7 +55,10 @@ def run(self):
delay(1*us)
t0 = now_mu()
self.loop_out.pulse(1*us)
self.set_dataset("rtt", mu_to_seconds(self.loop_in.timestamp_mu() - t0))
t1 = self.loop_in.timestamp_mu()
if t1 < 0:
raise PulseNotReceived()
self.set_dataset("rtt", mu_to_seconds(t1 - t0))


class ClockGeneratorLoopback(EnvExperiment):