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base repository: m-labs/artiq
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base: ffe4d81f3e3c
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head repository: m-labs/artiq
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compare: 1c9b8a1d522f
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Mar 20, 2016

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    1c9b8a1 View commit details
Showing with 5 additions and 7 deletions.
  1. +5 −7 artiq/test/coredevice/test_portability.py
12 changes: 5 additions & 7 deletions artiq/test/coredevice/test_portability.py
Original file line number Diff line number Diff line change
@@ -67,17 +67,15 @@ def build(self):
def _append(self, t, l, f):
if not hasattr(self.parent_test, "first_timestamp"):
self.parent_test.first_timestamp = t
self.parent_test.output_list.append(
(self.name, t-self.parent_test.first_timestamp, l, f))

def int_usec(self, mu):
return round(mu_to_seconds(mu, self.core)*1000000)
origin = self.parent_test.first_timestamp
t_usec = round(mu_to_seconds(t-origin, self.core)*1000000)
self.parent_test.output_list.append((self.name, t_usec, l, f))

def on(self, t, f):
self._append(self.int_usec(t), True, f)
self._append(t, True, f)

def off(self, t):
self._append(self.int_usec(t), False, 0)
self._append(t, False, 0)

@kernel
def pulse(self, f, duration):