analyzer: drive wishbone cyc signal

sbourdeauducq · sbourdeauducq · commit b5ec979db3a5 · 2016-03-15T19:46:12.000+08:00
diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py
@@ -175,6 +175,7 @@ def __init__(self, membus):
         # # #
 
         self.comb += [
+            membus.cyc.eq(self.sink.stb),
             membus.stb.eq(self.sink.stb),
             self.sink.ack.eq(membus.ack),
             membus.we.eq(1),
