analyzer: drive wishbone cyc signal

m-labs · Mar 15, 2016 · b5ec979 · b5ec979
1 parent a142d40
commit b5ec979
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py
@@ -175,6 +175,7 @@ def __init__(self, membus):
         # # #
 
         self.comb += [
+            membus.cyc.eq(self.sink.stb),
             membus.stb.eq(self.sink.stb),
             self.sink.ack.eq(membus.ack),
             membus.we.eq(1),