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base repository: m-labs/artiq
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base: 1bbef9406122
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head repository: m-labs/artiq
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compare: 6a9957a2ace4
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Mar 15, 2016

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    9ffaf82 View commit details
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    6a9957a View commit details
Showing with 4 additions and 2 deletions.
  1. +1 −1 artiq/coredevice/analyzer.py
  2. +3 −1 artiq/test/coredevice/test_analyzer.py
2 changes: 1 addition & 1 deletion artiq/coredevice/analyzer.py
Original file line number Diff line number Diff line change
@@ -327,7 +327,7 @@ def get_ref_period(devices):


def get_dds_sysclk(devices):
return get_single_device_argument(devices, "artiq.coredevice.core",
return get_single_device_argument(devices, "artiq.coredevice.dds",
"CoreDDS", "sysclk")


4 changes: 3 additions & 1 deletion artiq/test/coredevice/test_analyzer.py
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
from artiq.experiment import *
from artiq.coredevice.analyzer import decode_dump, OutputMessage, InputMessage
from artiq.coredevice.analyzer import (decode_dump, StoppedMessage,
OutputMessage, InputMessage)
from artiq.test.hardware_testbench import ExperimentCase


@@ -30,6 +31,7 @@ def test_ttl_pulse(self):
exp.run()

dump = decode_dump(comm.get_analyzer_dump())
self.assertIsInstance(dump.messages[-1], StoppedMessage)
output_messages = [msg for msg in dump.messages
if isinstance(msg, OutputMessage)
and msg.address == 0]