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base repository: m-labs/artiq
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head repository: m-labs/artiq
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compare: 85ea70a66471
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Mar 15, 2016

  1. analyzer: fix EOP generation

    @sbourdeauducq
    sbourdeauducq committed Mar 15, 2016
    Copy the full SHA
    62ac4e3 View commit details

  2. analyzer: fix byte_count

    @sbourdeauducq
    sbourdeauducq committed Mar 15, 2016
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    85ea70a View commit details
Showing with 11 additions and 12 deletions.
  1. +11 −12 artiq/gateware/rtio/analyzer.py
23 changes: 11 additions & 12 deletions artiq/gateware/rtio/analyzer.py
View file
Original file line number Diff line number Diff line change
@@ -135,6 +135,7 @@ def __init__(self, rtio_core, enable):
).Else(
self.source.data.eq(input_output.raw_bits())
),
self.source.eop.eq(0),
self.source.stb.eq(enable &
(input_output_stb | exception_stb)),

@@ -166,11 +167,9 @@ def __init__(self, membus):
alignment_bits=data_alignment)
self.byte_count = CSRStatus(32) # only read when shut down

sink_layout = [("data", dw)]
if messages_per_dw > 1:
sink_layout.append(("valid_token_count",
bits_for(messages_per_dw)))
self.sink = stream.Endpoint(sink_layout)
self.sink = stream.Endpoint(
[("data", dw),
("valid_token_count", bits_for(messages_per_dw))])

# # #

@@ -200,12 +199,13 @@ def __init__(self, membus):
)
]

event_counter = Signal(32)
message_count = Signal(32 - log2_int(message_len))
self.comb += self.byte_count.status.eq(
event_counter << data_alignment)
message_count << log2_int(message_len))
self.sync += [
If(self.reset.re, event_counter.eq(0)),
If(membus.ack, event_counter.eq(event_counter + 1))
If(self.reset.re, message_count.eq(0)),
If(membus.ack, message_count.eq(
message_count + self.sink.valid_token_count))
]


@@ -219,10 +219,9 @@ def __init__(self, rtio_core, membus, fifo_depth=128):
rtio_core, self.enable.storage)
self.submodules.fifo = stream.SyncFIFO(
[("data", message_len)], fifo_depth, True)
dw = len(membus.dat_w)
self.submodules.converter = stream.Converter(
message_len, dw, reverse=True,
report_valid_token_count=dw > message_len)
message_len, len(membus.dat_w), reverse=True,
report_valid_token_count=True)
self.submodules.dma = DMAWriter(membus)

enable_r = Signal()