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base repository: m-labs/artiq
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Mar 21, 2016

  1. pipistrello: sys_clk 83 -> 75 MHz 

    This should close #341 once migen generates stable output.
    @jordens
    jordens committed Mar 21, 2016
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    8f54a1e View commit details
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  1. +1 −0 artiq/gateware/targets/pipistrello.py
1 change: 1 addition & 0 deletions artiq/gateware/targets/pipistrello.py
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Original file line number Diff line number Diff line change
@@ -147,6 +147,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
l2_size=64*1024,
with_timer=False,
ident=artiq_version,
clk_freq=75*1000*1000,
**kwargs)
AMPSoC.__init__(self)