pipistrello: sys_clk 83 -> 75 MHz

This should close #341 once migen generates stable output.
m-labs · Mar 21, 2016 · 8f54a1e · 8f54a1e
1 parent 22cd12f
commit 8f54a1e
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
@@ -147,6 +147,7 @@ def __init__(self, cpu_type="or1k", **kwargs):
                          l2_size=64*1024,
                          with_timer=False,
                          ident=artiq_version,
+                         clk_freq=75*1000*1000,
                          **kwargs)
         AMPSoC.__init__(self)