add some debug counters on EDID

timvideos · Sep 8, 2015 · d040a09 · d040a09
1 parent 2b9a864
commit d040a09
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Showing 2 changed files with 65 additions and 2 deletions.
diff --git a/firmware/lm32/ci.c b/firmware/lm32/ci.c
@@ -60,6 +60,8 @@ static void help_debug(void)
 {
 	puts("debug pll                      - dump pll configuration");
 	puts("debug ddr                      - show DDR bandwidth");
+	puts("debug edid                     - show EDID debug counters");
+	puts("debug edid_reset               - reset EDID debug counters");
 }
 
 static void help(void)
@@ -341,6 +343,27 @@ static void debug_ddr(void)
 	printf("read:%5dMbps  write:%5dMbps  all:%5dMbps\n", rdb, wrb, rdb + wrb);
 }
 
+static void debug_edid(void)
+{
+	printf("hdmi_in0:\n");
+	printf("nwrites: %d\n", hdmi_in0_edid_debug_nwrites_read());
+	printf("nreads: %d\n", hdmi_in0_edid_debug_nreads_read());
+	printf("ninvalids: %d\n", hdmi_in0_edid_debug_ninvalids_read());
+	puts("");
+	printf("hdmi_in1:\n");
+	printf("nwrites: %d\n", hdmi_in1_edid_debug_nwrites_read());
+	printf("nreads: %d\n", hdmi_in1_edid_debug_nreads_read());
+	printf("ninvalids: %d\n", hdmi_in1_edid_debug_ninvalids_read());
+}
+
+static void debug_edid_reset(void)
+{
+	printf("Reseting EDID debug\n");
+	hdmi_in0_edid_debug_clear_write(1);
+	hdmi_in1_edid_debug_clear_write(1);
+}
+
+
 static char *readstr(void)
 {
 	char c[2];
@@ -533,6 +556,10 @@ void ci_service(void)
 			debug_pll();
 		else if(strcmp(token, "ddr") == 0)
 			debug_ddr();
+		else if(strcmp(token, "edid") == 0)
+			debug_edid();
+		else if(strcmp(token, "edid_reset") == 0)
+			debug_edid_reset();
 		else
 			help_debug();
 	} else {

diff --git a/hdl/hdmi_in/edid.py b/hdl/hdmi_in/edid.py
@@ -3,7 +3,7 @@
 from migen.genlib.cdc import MultiReg
 from migen.genlib.fsm import FSM, NextState
 from migen.genlib.misc import chooser
-from migen.bank.description import CSRStorage, CSRStatus, AutoCSR
+from migen.bank.description import CSR, CSRStorage, CSRStatus, AutoCSR
 
 _default_edid = [
     0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
@@ -117,13 +117,19 @@ def __init__(self, pads, default=_default_edid):
         fsm = FSM()
         self.submodules += fsm
 
+        # debug signals
+        debug_write = Signal()
+        debug_read = Signal()
+        debug_invalid = Signal()
+
         fsm.act("WAIT_START")
         fsm.act("RCV_ADDRESS",
             If(counter == 8,
                 If(din[1:] == 0x50,
                     update_is_read.eq(1),
                     NextState("ACK_ADDRESS0")
                 ).Else(
+                    debug_invalid.eq(1),
                     NextState("WAIT_START")
                 )
             )
@@ -161,7 +167,10 @@ def __init__(self, pads, default=_default_edid):
         )
         fsm.act("ACK_OFFSET2",
             zero_drv.eq(1),
-            If(~scl_i, NextState("RCV_ADDRESS"))
+            If(~scl_i,
+                debug_write.eq(1),
+                NextState("RCV_ADDRESS")
+            )
         )
 
         fsm.act("READ",
@@ -177,6 +186,7 @@ def __init__(self, pads, default=_default_edid):
         fsm.act("ACK_READ",
             If(scl_rising,
                 oc_inc.eq(1),
+                debug_read.eq(1),
                 If(sda_i,
                     NextState("WAIT_START")
                 ).Else(
@@ -188,3 +198,29 @@ def __init__(self, pads, default=_default_edid):
         for state in fsm.actions.keys():
             fsm.act(state, If(start, NextState("RCV_ADDRESS")))
             fsm.act(state, If(~self._hpd_en.storage, NextState("WAIT_START")))
+
+
+        # debug logic
+        self._debug_clear = CSR()
+        self._debug_nwrites = CSRStatus(16)
+        self._debug_nreads = CSRStatus(16)
+        self._debug_ninvalids = CSRStatus(16)
+
+        debug_clear = self._debug_clear.r & self._debug_clear.re
+        debug_nwrites = self._debug_nwrites.status
+        debug_nreads = self._debug_nreads.status
+        debug_ninvalids = self._debug_ninvalids.status
+
+        self.sync += [
+            If(debug_clear,
+                debug_nwrites.eq(0),
+                debug_nreads.eq(0),
+                debug_ninvalids.eq(0)
+            ).Elif(debug_write,
+                debug_nwrites.eq(debug_nwrites + 1)
+            ).Elif(debug_read,
+                debug_nreads.eq(debug_nreads + 1)
+            ).Elif(debug_invalid,
+                debug_ninvalids.eq(debug_ninvalids + 1)
+            )
+        ]