targets: prepare atlys_edid_debug for debugging EDID signals with Lit…

…eScope
timvideos · Sep 8, 2015 · 168e844 · 168e844
1 parent d040a09
commit 168e844
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Showing 4 changed files with 95 additions and 8 deletions.
diff --git a/platforms/atlys.py b/platforms/atlys.py
@@ -113,14 +113,14 @@
     # NET "sw<5>" LOC = "R5";  # Bank = 2, Pin name = IO_L48P_D7,             Sch name = SW5
     # NET "sw<6>" LOC = "T5";  # Bank = 2, Pin name = IO_L48N_RDWR_B_VREF_2,  Sch name = SW6
     # NET "sw<7>" LOC = "E4";  # Bank = 3, Pin name = IO_L54P_M3RESET,        Sch name = SW7
-    ("user_dip", 0, Pins("A10"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
-    ("user_dip", 1, Pins("D14"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
-    ("user_dip", 2, Pins("C14"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
-    ("user_dip", 3, Pins("P15"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
-    ("user_dip", 4, Pins("P12"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
-    ("user_dip", 5, Pins("R5"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
-    ("user_dip", 6, Pins("T5"), Misc("PULLDOWN"), IOStandard("LVCMOS33")),
-    ("user_dip", 7, Pins("E4"), Misc("PULLDOWN"), IOStandard("LVCMOS18")),
+    ("user_dip", 0, Pins("A10"), IOStandard("LVCMOS33")),
+    ("user_dip", 1, Pins("D14"), IOStandard("LVCMOS33")),
+    ("user_dip", 2, Pins("C14"), IOStandard("LVCMOS33")),
+    ("user_dip", 3, Pins("P15"), IOStandard("LVCMOS33")),
+    ("user_dip", 4, Pins("P12"), IOStandard("LVCMOS33")),
+    ("user_dip", 5, Pins("R5"), IOStandard("LVCMOS33")),
+    ("user_dip", 6, Pins("T5"), IOStandard("LVCMOS33")),
+    ("user_dip", 7, Pins("E4"), IOStandard("LVCMOS18")),
 
     ## TEMAC Ethernet MAC - FIXME
     # 10/100/1000 Ethernet PHY

diff --git a/targets/atlys_edid_debug.py b/targets/atlys_edid_debug.py
@@ -0,0 +1,47 @@
+from targets.atlys_hdmi2usb import *
+
+from misoclib.com.uart.phy import UARTPHY
+from misoclib.com import uart
+from misoclib.tools.wishbone import WishboneStreamingBridge
+
+class UARTVirtualPhy:
+    def __init__(self):
+        self.sink = Sink([("data", 8)])
+        self.source = Source([("data", 8)])
+
+
+class EDIDDebugSoC(VideomixerSoC):
+    def __init__(self, platform, with_uart=False, **kwargs):
+        VideomixerSoC.__init__(self, platform, with_uart=with_uart, **kwargs)
+
+        uart_sel = platform.request("user_dip", 0)
+        self.comb += platform.request("user_led", 0).eq(uart_sel)
+
+        self.submodules.uart_phy = UARTPHY(platform.request("serial"), self.clk_freq, 115200)
+        uart_phys = {
+            "cpu": UARTVirtualPhy(),
+            "bridge": UARTVirtualPhy()
+        }
+        self.comb += [
+            If(uart_sel,
+                Record.connect(self.uart_phy.source, uart_phys["bridge"].source),
+                Record.connect(uart_phys["bridge"].sink, self.uart_phy.sink),
+                uart_phys["cpu"].source.ack.eq(1) # avoid stalling cpu
+            ).Else(
+                Record.connect(self.uart_phy.source, uart_phys["cpu"].source),
+                Record.connect(uart_phys["cpu"].sink, self.uart_phy.sink),
+                uart_phys["bridge"].source.ack.eq(1) # avoid stalling bridge
+            )
+        ]
+
+        # UART cpu
+        self.submodules.uart = uart.UART(uart_phys["cpu"])
+
+        # UART bridge
+        self.submodules.bridge = WishboneStreamingBridge(uart_phys["bridge"], self.clk_freq)
+        self.add_wb_master(self.bridge.wishbone)
+
+        # XXX add LiteScope on EDID lines
+
+
+default_subtarget = EDIDDebugSoC
diff --git a/test/edid_debug/make.py b/test/edid_debug/make.py
@@ -0,0 +1,31 @@
+#!/usr/bin/env python3
+import argparse
+import importlib
+
+
+def _get_args():
+    parser = argparse.ArgumentParser()
+    parser.add_argument("-b", "--bridge", default="uart", help="Bridge to use")
+    parser.add_argument("--port", default="3", help="UART port")
+    parser.add_argument("--baudrate", default=115200, help="UART baudrate")
+    parser.add_argument("--busword", default=8, help="CSR busword")
+
+    parser.add_argument("test", nargs="+", help="specify a test")
+
+    return parser.parse_args()
+
+if __name__ == "__main__":
+    args = _get_args()
+    if args.bridge == "uart":
+        from misoclib.com.uart.software.wishbone import UARTWishboneBridgeDriver
+        port = args.port if not args.port.isdigit() else int(args.port)
+        wb = UARTWishboneBridgeDriver(port, args.baudrate, "../csr.csv", int(args.busword), debug=False)
+    else:
+        ValueError("Invalid bridge {}".format(args.bridge))
+
+    def _import(name):
+        return importlib.import_module(name)
+
+    for test in args.test:
+        t = _import(test)
+        t.main(wb)
diff --git a/test/edid_debug/test_regs.py b/test/edid_debug/test_regs.py
@@ -0,0 +1,9 @@
+def main(wb):
+    wb.open()
+    regs = wb.regs
+    # # #
+    print("sysid     : 0x{:04x}".format(regs.identifier_sysid.read()))
+    print("revision  : 0x{:04x}".format(regs.identifier_revision.read()))
+    print("frequency : {}MHz".format(int(regs.identifier_frequency.read()/1000000)))
+    # # #
+    wb.close()