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targets/atlys_edid_debug: add LiteScope for EDID debug (working, now …
…we have to analyze things)
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enjoy-digital committed Sep 9, 2015
1 parent 92197a0 commit 6b5f66c
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Showing 4 changed files with 66 additions and 67 deletions.
27 changes: 0 additions & 27 deletions firmware/lm32/ci.c
Expand Up @@ -60,8 +60,6 @@ static void help_debug(void)
{
puts("debug pll - dump pll configuration");
puts("debug ddr - show DDR bandwidth");
puts("debug edid - show EDID debug counters");
puts("debug edid_reset - reset EDID debug counters");
}

static void help(void)
Expand Down Expand Up @@ -343,27 +341,6 @@ static void debug_ddr(void)
printf("read:%5dMbps write:%5dMbps all:%5dMbps\n", rdb, wrb, rdb + wrb);
}

static void debug_edid(void)
{
printf("hdmi_in0:\n");
printf("nwrites: %d\n", hdmi_in0_edid_debug_nwrites_read());
printf("nreads: %d\n", hdmi_in0_edid_debug_nreads_read());
printf("ninvalids: %d\n", hdmi_in0_edid_debug_ninvalids_read());
puts("");
printf("hdmi_in1:\n");
printf("nwrites: %d\n", hdmi_in1_edid_debug_nwrites_read());
printf("nreads: %d\n", hdmi_in1_edid_debug_nreads_read());
printf("ninvalids: %d\n", hdmi_in1_edid_debug_ninvalids_read());
}

static void debug_edid_reset(void)
{
printf("Reseting EDID debug\n");
hdmi_in0_edid_debug_clear_write(1);
hdmi_in1_edid_debug_clear_write(1);
}


static char *readstr(void)
{
char c[2];
Expand Down Expand Up @@ -556,10 +533,6 @@ void ci_service(void)
debug_pll();
else if(strcmp(token, "ddr") == 0)
debug_ddr();
else if(strcmp(token, "edid") == 0)
debug_edid();
else if(strcmp(token, "edid_reset") == 0)
debug_edid_reset();
else
help_debug();
} else {
Expand Down
52 changes: 13 additions & 39 deletions hdl/hdmi_in/edid.py
Expand Up @@ -3,7 +3,7 @@
from migen.genlib.cdc import MultiReg
from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import chooser
from migen.bank.description import CSR, CSRStorage, CSRStatus, AutoCSR
from migen.bank.description import CSRStorage, CSRStatus, AutoCSR

_default_edid = [
0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x3D, 0x17, 0x32, 0x12, 0x2A, 0x6A, 0xBF, 0x00,
Expand Down Expand Up @@ -46,6 +46,13 @@ def __init__(self, pads, default=_default_edid):
MultiReg(_sda_i_async, sda_i)
]

# for debug
self.scl = scl_raw
self.sda_i = sda_i
self.sda_o = Signal()
self.comb += self.sda_o.eq(~_sda_drv_reg)
self.sda_oe = _sda_drv_reg

scl_i = Signal()
samp_count = Signal(6)
samp_carry = Signal()
Expand Down Expand Up @@ -86,6 +93,9 @@ def __init__(self, pads, default=_default_edid):
)
]

self.din = din
self.counter = counter

is_read = Signal()
update_is_read = Signal()
self.sync += If(update_is_read, is_read.eq(din[0]))
Expand Down Expand Up @@ -114,13 +124,7 @@ def __init__(self, pads, default=_default_edid):
self.sync += If(data_drv_en, data_drv.eq(1)).Elif(data_drv_stop, data_drv.eq(0))
self.sync += If(data_drv_en, chooser(rdport.dat_r, counter, data_bit, 8, reverse=True))

fsm = FSM()
self.submodules += fsm

# debug signals
debug_write = Signal()
debug_read = Signal()
debug_invalid = Signal()
self.submodules.fsm = fsm = FSM()

fsm.act("WAIT_START")
fsm.act("RCV_ADDRESS",
Expand All @@ -129,7 +133,6 @@ def __init__(self, pads, default=_default_edid):
update_is_read.eq(1),
NextState("ACK_ADDRESS0")
).Else(
debug_invalid.eq(1),
NextState("WAIT_START")
)
)
Expand Down Expand Up @@ -167,10 +170,7 @@ def __init__(self, pads, default=_default_edid):
)
fsm.act("ACK_OFFSET2",
zero_drv.eq(1),
If(~scl_i,
debug_write.eq(1),
NextState("RCV_ADDRESS")
)
If(~scl_i, NextState("RCV_ADDRESS"))
)

fsm.act("READ",
Expand All @@ -186,7 +186,6 @@ def __init__(self, pads, default=_default_edid):
fsm.act("ACK_READ",
If(scl_rising,
oc_inc.eq(1),
debug_read.eq(1),
If(sda_i,
NextState("WAIT_START")
).Else(
Expand All @@ -199,28 +198,3 @@ def __init__(self, pads, default=_default_edid):
fsm.act(state, If(start, NextState("RCV_ADDRESS")))
fsm.act(state, If(~self._hpd_en.storage, NextState("WAIT_START")))


# debug logic
self._debug_clear = CSR()
self._debug_nwrites = CSRStatus(16)
self._debug_nreads = CSRStatus(16)
self._debug_ninvalids = CSRStatus(16)

debug_clear = self._debug_clear.r & self._debug_clear.re
debug_nwrites = self._debug_nwrites.status
debug_nreads = self._debug_nreads.status
debug_ninvalids = self._debug_ninvalids.status

self.sync += [
If(debug_clear,
debug_nwrites.eq(0),
debug_nreads.eq(0),
debug_ninvalids.eq(0)
).Elif(debug_write,
debug_nwrites.eq(debug_nwrites + 1)
).Elif(debug_read,
debug_nreads.eq(debug_nreads + 1)
).Elif(debug_invalid,
debug_ninvalids.eq(debug_ninvalids + 1)
)
]
31 changes: 30 additions & 1 deletion targets/atlys_edid_debug.py
Expand Up @@ -4,13 +4,22 @@
from misoclib.com import uart
from misoclib.tools.wishbone import WishboneStreamingBridge

from litescope.common import *
from litescope.core.port import LiteScopeTerm
from litescope.frontend.la import LiteScopeLA

class UARTVirtualPhy:
def __init__(self):
self.sink = Sink([("data", 8)])
self.source = Source([("data", 8)])


class EDIDDebugSoC(VideomixerSoC):
csr_map = {
"la": 30
}
csr_map.update(VideomixerSoC.csr_map)

def __init__(self, platform, with_uart=False, **kwargs):
VideomixerSoC.__init__(self, platform, with_uart=with_uart, **kwargs)

Expand Down Expand Up @@ -41,7 +50,27 @@ def __init__(self, platform, with_uart=False, **kwargs):
self.submodules.bridge = WishboneStreamingBridge(uart_phys["bridge"], self.clk_freq)
self.add_wb_master(self.bridge.wishbone)

# XXX add LiteScope on EDID lines
# LiteScope on EDID lines and fsm
self.hdmi_in0_edid_fsm_state = Signal(4)
self.debug = (
self.hdmi_in0.edid.scl,
self.hdmi_in0.edid.sda_i,
self.hdmi_in0.edid.sda_o,
self.hdmi_in0.edid.sda_oe,
self.hdmi_in0.edid.counter,
self.hdmi_in0.edid.din,
self.hdmi_in0_edid_fsm_state
)
self.submodules.la = LiteScopeLA(self.debug, 32*1024, with_subsampler=True)
self.la.trigger.add_port(LiteScopeTerm(self.la.dw))

def do_finalize(self):
VideomixerSoC.do_finalize(self)
self.comb += [
self.hdmi_in0_edid_fsm_state.eq(self.hdmi_in0.edid.fsm.state)
]

def do_exit(self, vns):
self.la.export(vns, "../../test/edid_debug/la.csv") # XXX

default_subtarget = EDIDDebugSoC
23 changes: 23 additions & 0 deletions test/edid_debug/test_la.py
@@ -0,0 +1,23 @@
from litescope.software.driver.la import LiteScopeLADriver


def main(wb):
wb.open()
# # #
la = LiteScopeLADriver(wb.regs, "la", debug=True)

# cond = {"hdmi_in0_edid_scl_raw" : 0}
cond = {"hdmi_in0_edid_fsm_state" : 2}
# cond = {}
la.configure_term(port=0, cond=cond)
la.configure_sum("term")
la.configure_subsampler(64)
la.run(offset=128, length=8192)

while not la.done():
pass
la.upload()

la.save("dump.vcd")
# # #
wb.close()

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