hdmi_in/edid: fix sda sampling: need to be similar to scl otherwise o…

…n sources with fast scl we were detecting false starts
timvideos · Sep 9, 2015 · 9bb88b8 · 9bb88b8
1 parent 6b5f66c
commit 9bb88b8
Showing 1 changed file with 6 additions and 2 deletions.
diff --git a/hdl/hdmi_in/edid.py b/hdl/hdmi_in/edid.py
@@ -36,14 +36,15 @@ def __init__(self, pads, default=_default_edid):
         # EDID
         scl_raw = Signal()
         sda_i = Signal()
+        sda_raw = Signal()
         sda_drv = Signal()
         _sda_drv_reg = Signal()
         _sda_i_async = Signal()
         self.sync += _sda_drv_reg.eq(sda_drv)
         self.specials += [
             MultiReg(pads.scl, scl_raw),
             Tristate(pads.sda, 0, _sda_drv_reg, _sda_i_async),
-            MultiReg(_sda_i_async, sda_i)
+            MultiReg(_sda_i_async, sda_raw)
         ]
 
         # for debug
@@ -58,7 +59,10 @@ def __init__(self, pads, default=_default_edid):
         samp_carry = Signal()
         self.sync += [
             Cat(samp_count, samp_carry).eq(samp_count + 1),
-            If(samp_carry, scl_i.eq(scl_raw))
+            If(samp_carry,
+                scl_i.eq(scl_raw),
+                sda_i.eq(sda_raw)
+            )
         ]
 
         scl_r = Signal()