Fixing the hdmi2ethernet.

timvideos · Sep 13, 2015 · 894bfff · 894bfff
1 parent fbb9403
commit 894bfff
Showing 1 changed file with 36 additions and 16 deletions.
diff --git a/targets/atlys_hdmi2ethernet.py b/targets/atlys_hdmi2ethernet.py
@@ -6,8 +6,8 @@
 from liteeth.core import LiteEthUDPIPCore
 from liteeth.frontend.etherbone import LiteEthEtherbone
 
-from hdl import hdmi_in
-from hdl import hdmi_out
+from hdl.hdmi_in import HDMIIn
+from hdl.hdmi_out import HDMIOut
 from hdl.encoder import EncoderReader, Encoder
 from hdl.streamer import UDPStreamer
 
@@ -54,36 +54,56 @@ def __init__(self, platform,
 
 class VideomixerSoC(EtherboneSoC):
     csr_map = {
-        "fb":                  20,
-        "dvisampler":          21,
-        "dvisampler_edid_mem": 22,
+        "hdmi_out0":         20,
+        "hdmi_out1":         21,
+        "hdmi_in0":          22,
+        "hdmi_in0_edid_mem": 23,
+        "hdmi_in1":          24,
+        "hdmi_in1_edid_mem": 25,
     }
     csr_map.update(EtherboneSoC.csr_map)
 
     interrupt_map = {
-        "dvisampler": 3,
+        "hdmi_in0": 3,
+        "hdmi_in1": 4,
     }
     interrupt_map.update(EtherboneSoC.interrupt_map)
 
     def __init__(self, platform, **kwargs):
         EtherboneSoC.__init__(self, platform, **kwargs)
-        self.submodules.hdmi_in0 = HDMIIn(platform.request("dvi_in", 1),
+        self.submodules.hdmi_in0 = HDMIIn(platform.request("hdmi_in", 0),
                                           self.sdram.crossbar.get_master(),
-                                          fifo_depth=512)
-        self.submodules.hdmi_out0 = HDMIOut(platform.request("hdmi_out"),
+                                          fifo_depth=1024)
+        self.submodules.hdmi_in1 = HDMIIn(platform.request("hdmi_in", 1),
+                                          self.sdram.crossbar.get_master(),
+                                          fifo_depth=1024)
+        self.submodules.hdmi_out0 = HDMIOut(platform.request("hdmi_out", 0),
                                             self.sdram.crossbar.get_master())
+        self.submodules.hdmi_out1 = HDMIOut(platform.request("hdmi_out", 1),
+                                            self.sdram.crossbar.get_master(),
+                                            self.hdmi_out0.driver.clocking) # share clocking with hdmi_out0
+                                                                            # since no PLL_ADV left.
+
+        platform.add_platform_command("""INST PLL_ADV LOC=PLL_ADV_X0Y0;""") # all PLL_ADV are used: router needs help...
         platform.add_platform_command("""PIN "hdmi_out_pix_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
+        platform.add_platform_command("""PIN "hdmi_out_pix_bufg_1.O" CLOCK_DEDICATED_ROUTE = FALSE;""")
         platform.add_platform_command("""
-NET "{pix_clk}" TNM_NET = "GRPpix_clk";
-TIMESPEC "TSise_sucks7" = FROM "GRPpix_clk" TO "GRPsys_clk" TIG;
-TIMESPEC "TSise_sucks8" = FROM "GRPsys_clk" TO "GRPpix_clk" TIG;
-""", pix_clk=self.hdmi_out0.driver.clocking.cd_pix.clk)
-
+NET "{pix0_clk}" TNM_NET = "GRPpix0_clk";
+NET "{pix1_clk}" TNM_NET = "GRPpix1_clk";
+TIMESPEC "TSise_sucks7" = FROM "GRPpix0_clk" TO "GRPsys_clk" TIG;
+TIMESPEC "TSise_sucks8" = FROM "GRPsys_clk" TO "GRPpix0_clk" TIG;
+TIMESPEC "TSise_sucks9" = FROM "GRPpix1_clk" TO "GRPsys_clk" TIG;
+TIMESPEC "TSise_sucks10" = FROM "GRPsys_clk" TO "GRPpix1_clk" TIG;
+""", pix0_clk=self.hdmi_out0.driver.clocking.cd_pix.clk,
+     pix1_clk=self.hdmi_out1.driver.clocking.cd_pix.clk,
+)
+        for k, v in platform.hdmi_infos.items():
+            self.add_constant(k, v)
 
 class HDMI2EthernetSoC(VideomixerSoC):
     csr_map = {
-        "encoder_reader": 23,
-        "encoder"       : 24,
+        "encoder_reader": 26,
+        "encoder":        27,
     }
     csr_map.update(VideomixerSoC.csr_map)
     mem_map = {