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drtio: fix FullMemoryWE usage
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sbourdeauducq committed Nov 23, 2016
1 parent 0c49679 commit e532261
Showing 1 changed file with 3 additions and 2 deletions.
5 changes: 3 additions & 2 deletions artiq/gateware/drtio/aux_controller.py
Original file line number Diff line number Diff line change
@@ -205,14 +205,15 @@ def __init__(self, link_layer, min_mem_dw):
)


# TODO: FullMemoryWE should be applied by migen.build
@FullMemoryWE()
class AuxController(Module):
def __init__(self, link_layer):
self.bus = wishbone.Interface()
self.submodules.transmitter = Transmitter(link_layer, len(self.bus.dat_w))
self.submodules.receiver = Receiver(link_layer, len(self.bus.dat_w))

# TODO: FullMemoryWE should be applied by migen.build
tx_sdram_if = FullMemoryWE()(wishbone.SRAM(self.transmitter.mem, read_only=False))
tx_sdram_if = wishbone.SRAM(self.transmitter.mem, read_only=False)
rx_sdram_if = wishbone.SRAM(self.receiver.mem, read_only=True)
wsb = log2_int(len(self.bus.dat_w)//8)
decoder = wishbone.Decoder(self.bus,

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