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  • 7 commits
  • 26 files changed
  • 2 contributors

Commits on Nov 21, 2016

  1. runtime: rewrite rtio support code in Rust.

    whitequark committed Nov 21, 2016
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    a825584 View commit details
  2. runtime: rewrite i2c support code in Rust.

    whitequark committed Nov 21, 2016
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    18b7cce View commit details
  3. compiler: disable remarks.

    whitequark committed Nov 21, 2016
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    ac997da View commit details
  4. Copy the full SHA
    1d1e821 View commit details

Commits on Nov 22, 2016

  1. Copy the full SHA
    7498c8b View commit details
  2. Copy the full SHA
    0aaf120 View commit details
  3. Copy the full SHA
    9acc7d1 View commit details
2 changes: 1 addition & 1 deletion artiq/compiler/module.py
Original file line number Diff line number Diff line change
@@ -40,7 +40,7 @@ def from_filename(cls, filename, engine=None):
return cls(source.Buffer(f.read(), filename, 1), engine=engine)

class Module:
def __init__(self, src, ref_period=1e-6, attribute_writeback=True, remarks=True):
def __init__(self, src, ref_period=1e-6, attribute_writeback=True, remarks=False):
self.attribute_writeback = attribute_writeback
self.engine = src.engine
self.embedding_map = src.embedding_map
3 changes: 1 addition & 2 deletions artiq/coredevice/rtio.py
Original file line number Diff line number Diff line change
@@ -3,8 +3,7 @@


@syscall(flags={"nowrite"})
def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32
) -> TNone:
def rtio_output(time_mu: TInt64, channel: TInt32, addr: TInt32, data: TInt32) -> TNone:
raise NotImplementedError("syscall not simulated")


4 changes: 1 addition & 3 deletions artiq/gateware/drtio/core.py
Original file line number Diff line number Diff line change
@@ -57,13 +57,11 @@ def __init__(self, transceiver, channel_count=1024, fine_ts_width=3):
self.submodules.rt_controller = rt_controller.RTController(
self.rt_packets, channel_count, fine_ts_width)
self.submodules.rt_manager = rt_controller.RTManager(self.rt_packets)
self.cri = self.rt_controller.cri

self.submodules.aux_controller = aux_controller.AuxController(
self.link_layer)

def get_kernel_csrs(self):
return self.rt_controller.get_kernel_csrs()

def get_csrs(self):
return (self.link_layer.get_csrs() +
self.rt_controller.get_csrs() +
33 changes: 15 additions & 18 deletions artiq/gateware/drtio/rt_controller.py
Original file line number Diff line number Diff line change
@@ -5,7 +5,7 @@
from misoc.interconnect.csr import *

from artiq.gateware.rtio.cdc import RTIOCounter
from artiq.gateware.rtio.kernel_csrs import KernelCSRs
from artiq.gateware.rtio import cri


class _CSRs(AutoCSR):
@@ -27,20 +27,20 @@ def __init__(self):

class RTController(Module):
def __init__(self, rt_packets, channel_count, fine_ts_width):
self.kcsrs = KernelCSRs()
self.csrs = _CSRs()
self.cri = cri.Interface()
self.comb += self.cri.arb_gnt.eq(1)

# channel selection
chan_sel = Signal(16)
self.comb += chan_sel.eq(
Mux(self.csrs.chan_sel_override_en.storage,
self.csrs.chan_sel_override.storage,
self.kcsrs.chan_sel.storage))
self.cri.chan_sel[:16]))

# master RTIO counter and counter synchronization
self.submodules.counter = RTIOCounter(64-fine_ts_width)
self.sync += If(self.kcsrs.counter_update.re,
self.kcsrs.counter.status.eq(self.counter.value_sys << fine_ts_width))
self.comb += self.cri.counter.eq(self.counter.value_sys << fine_ts_width)
tsc_correction = Signal(64)
self.csrs.tsc_correction.storage.attr.add("no_retiming")
self.specials += MultiReg(self.csrs.tsc_correction.storage, tsc_correction)
@@ -67,14 +67,14 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
self.comb += [
fifo_spaces.adr.eq(chan_sel),
last_timestamps.adr.eq(chan_sel),
last_timestamps.dat_w.eq(self.kcsrs.o_timestamp.storage),
last_timestamps.dat_w.eq(self.cri.o_timestamp),
rt_packets.write_channel.eq(chan_sel),
rt_packets.write_address.eq(self.kcsrs.o_address.storage),
rt_packets.write_data.eq(self.kcsrs.o_data.storage),
rt_packets.write_address.eq(self.cri.o_address),
rt_packets.write_data.eq(self.cri.o_data),
If(rt_packets_fifo_request,
rt_packets.write_timestamp.eq(0xffff000000000000)
).Else(
rt_packets.write_timestamp.eq(self.kcsrs.o_timestamp.storage)
rt_packets.write_timestamp.eq(self.cri.o_timestamp)
)
]

@@ -85,15 +85,15 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
status_underflow = Signal()
status_sequence_error = Signal()
self.comb += [
self.kcsrs.o_status.status.eq(Cat(
self.cri.o_status.eq(Cat(
status_wait, status_underflow, status_sequence_error)),
self.csrs.o_wait.status.eq(status_wait)
]
sequence_error_set = Signal()
underflow_set = Signal()
self.sync += [
If(self.kcsrs.o_underflow_reset.re, status_underflow.eq(0)),
If(self.kcsrs.o_sequence_error_reset.re, status_sequence_error.eq(0)),
If(self.cri.cmd == cri.commands["o_underflow_reset"], status_underflow.eq(0)),
If(self.cri.cmd == cri.commands["o_sequence_error_reset"], status_sequence_error.eq(0)),
If(underflow_set, status_underflow.eq(1)),
If(sequence_error_set, status_sequence_error.eq(1)),
]
@@ -107,14 +107,14 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
self.submodules += timeout_counter

# TODO: collision, replace, busy
cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r
cond_underflow = ((self.kcsrs.o_timestamp.storage[fine_ts_width:]
cond_sequence_error = self.cri.o_timestamp < last_timestamps.dat_r
cond_underflow = ((self.cri.o_timestamp[fine_ts_width:]
- self.csrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys)
cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:] < self.counter.value_sys)
& (last_timestamps.dat_r != 0))

fsm.act("IDLE",
If(self.kcsrs.o_we.re,
If(self.cri.cmd == cri.commands["write"],
If(cond_sequence_error,
sequence_error_set.eq(1)
).Elif(cond_underflow,
@@ -184,9 +184,6 @@ def __init__(self, rt_packets, channel_count, fine_ts_width):
)
]

def get_kernel_csrs(self):
return self.kcsrs.get_csrs()

def get_csrs(self):
return self.csrs.get_csrs()

3 changes: 2 additions & 1 deletion artiq/gateware/rtio/__init__.py
Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
from artiq.gateware.rtio.core import Channel, LogChannel, RTIO
from artiq.gateware.rtio.cri import KernelInitiator
from artiq.gateware.rtio.core import Channel, LogChannel, Core
from artiq.gateware.rtio.analyzer import Analyzer
from artiq.gateware.rtio.moninj import MonInj
51 changes: 11 additions & 40 deletions artiq/gateware/rtio/analyzer.py
Original file line number Diff line number Diff line change
@@ -42,35 +42,23 @@


class MessageEncoder(Module, AutoCSR):
def __init__(self, rtio_core, enable):
def __init__(self, kcsrs, rtio_counter, enable):
self.source = stream.Endpoint([("data", message_len)])

self.overflow = CSRStatus()
self.overflow_reset = CSR()

# # #

kcsrs = rtio_core.kcsrs

input_output_stb = Signal()
input_output = Record(input_output_layout)
if hasattr(kcsrs, "o_data"):
o_data = kcsrs.o_data.storage
else:
o_data = 0
if hasattr(kcsrs, "o_address"):
o_address = kcsrs.o_address.storage
else:
o_address = 0
if hasattr(kcsrs, "i_data"):
i_data = kcsrs.i_data.status
else:
i_data = 0
o_data = kcsrs.o_data.storage
o_address = kcsrs.o_address.storage
i_data = kcsrs.i_data.status
self.comb += [
input_output.channel.eq(kcsrs.chan_sel.storage),
input_output.address_padding.eq(o_address),
input_output.rtio_counter.eq(
rtio_core.counter.value_sys << rtio_core.fine_ts_width),
input_output.rtio_counter.eq(rtio_counter),
If(kcsrs.o_we.re,
input_output.message_type.eq(MessageType.output.value),
input_output.timestamp.eq(kcsrs.o_timestamp.storage),
@@ -88,39 +76,22 @@ def __init__(self, rtio_core, enable):
self.comb += [
exception.message_type.eq(MessageType.exception.value),
exception.channel.eq(kcsrs.chan_sel.storage),
exception.rtio_counter.eq(
rtio_core.counter.value_sys << rtio_core.fine_ts_width),
exception.rtio_counter.eq(rtio_counter),
]
for ename in ("o_underflow_reset", "o_sequence_error_reset",
for ename in ("reset", "reset_phy",
"o_underflow_reset", "o_sequence_error_reset",
"o_collision_reset", "i_overflow_reset"):
self.comb += \
If(getattr(kcsrs, ename).re,
exception_stb.eq(1),
exception.exception_type.eq(
getattr(ExceptionType, ename).value)
)
for rname in "reset", "reset_phy":
r_d = Signal(reset=1)
r = getattr(kcsrs, rname).storage
self.sync += r_d.eq(r)
self.comb += [
If(r & ~r_d,
exception_stb.eq(1),
exception.exception_type.eq(
getattr(ExceptionType, rname+"_rising").value)
),
If(~r & r_d,
exception_stb.eq(1),
exception.exception_type.eq(
getattr(ExceptionType, rname+"_falling").value)
)
]

stopped = Record(stopped_layout)
self.comb += [
stopped.message_type.eq(MessageType.stopped.value),
stopped.rtio_counter.eq(
rtio_core.counter.value_sys << rtio_core.fine_ts_width),
stopped.rtio_counter.eq(rtio_counter),
]

enable_r = Signal()
@@ -210,13 +181,13 @@ def __init__(self, membus):


class Analyzer(Module, AutoCSR):
def __init__(self, rtio_core, membus, fifo_depth=128):
def __init__(self, kcsrs, rtio_counter, membus, fifo_depth=128):
# shutdown procedure: set enable to 0, wait until busy=0
self.enable = CSRStorage()
self.busy = CSRStatus()

self.submodules.message_encoder = MessageEncoder(
rtio_core, self.enable.storage)
kcsrs, rtio_counter, self.enable.storage)
self.submodules.fifo = stream.SyncFIFO(
[("data", message_len)], fifo_depth, True)
self.submodules.converter = stream.Converter(
77 changes: 36 additions & 41 deletions artiq/gateware/rtio/core.py
Original file line number Diff line number Diff line change
@@ -6,8 +6,7 @@
from migen.genlib.fifo import AsyncFIFO
from migen.genlib.resetsync import AsyncResetSynchronizer

from artiq.gateware.rtio import rtlink
from artiq.gateware.rtio.kernel_csrs import KernelCSRs
from artiq.gateware.rtio import cri, rtlink
from artiq.gateware.rtio.cdc import *


@@ -265,7 +264,7 @@ def __init__(self):
self.overrides = []


class RTIO(Module):
class Core(Module):
def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
data_width = max(rtlink.get_data_width(c.interface)
for c in channels)
@@ -278,35 +277,43 @@ def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
self.address_width = address_width
self.fine_ts_width = fine_ts_width

self.kcsrs = KernelCSRs()
self.cri = cri.Interface()
self.comb += self.cri.arb_gnt.eq(1)

# Clocking/Reset
# Create rsys, rio and rio_phy domains based on sys and rtio
# with reset controlled by CSR.
# with reset controlled by CRI.
cmd_reset = Signal(reset=1)
cmd_reset_phy = Signal(reset=1)
self.sync += [
cmd_reset.eq(self.cri.cmd == cri.commands["reset"]),
cmd_reset_phy.eq(self.cri.cmd == cri.commands["reset_phy"])
]
cmd_reset.attr.add("no_retiming")
cmd_reset_phy.attr.add("no_retiming")

self.clock_domains.cd_rsys = ClockDomain()
self.clock_domains.cd_rio = ClockDomain()
self.clock_domains.cd_rio_phy = ClockDomain()
self.comb += [
self.cd_rsys.clk.eq(ClockSignal()),
self.cd_rsys.rst.eq(self.kcsrs.reset.storage)
self.cd_rsys.rst.eq(cmd_reset)
]
self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
self.specials += AsyncResetSynchronizer(
self.cd_rio,
self.kcsrs.reset.storage | ResetSignal("rtio",
allow_reset_less=True))
cmd_reset | ResetSignal("rtio", allow_reset_less=True))
self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
self.specials += AsyncResetSynchronizer(
self.cd_rio_phy,
self.kcsrs.reset_phy.storage | ResetSignal("rtio",
allow_reset_less=True))
cmd_reset_phy | ResetSignal("rtio", allow_reset_less=True))

# Managers
self.submodules.counter = RTIOCounter(full_ts_width - fine_ts_width)

i_datas, i_timestamps = [], []
o_statuses, i_statuses = [], []
sel = self.kcsrs.chan_sel.storage
sel = self.cri.chan_sel[:16]
for n, channel in enumerate(channels):
if isinstance(channel, LogChannel):
i_datas.append(0)
@@ -322,30 +329,27 @@ def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
self.submodules += o_manager

if hasattr(o_manager.ev, "data"):
self.comb += o_manager.ev.data.eq(
self.kcsrs.o_data.storage)
self.comb += o_manager.ev.data.eq(self.cri.o_data)
if hasattr(o_manager.ev, "address"):
self.comb += o_manager.ev.address.eq(
self.kcsrs.o_address.storage)
ts_shift = (len(self.kcsrs.o_timestamp.storage)
- len(o_manager.ev.timestamp))
self.comb += o_manager.ev.timestamp.eq(
self.kcsrs.o_timestamp.storage[ts_shift:])
self.comb += o_manager.ev.address.eq(self.cri.o_address)
ts_shift = len(self.cri.o_timestamp) - len(o_manager.ev.timestamp)
self.comb += o_manager.ev.timestamp.eq(self.cri.o_timestamp[ts_shift:])

self.comb += o_manager.we.eq(selected & self.kcsrs.o_we.re)
self.comb += o_manager.we.eq(selected &
(self.cri.cmd == cri.commands["write"]))

underflow = Signal()
sequence_error = Signal()
collision = Signal()
busy = Signal()
self.sync.rsys += [
If(selected & self.kcsrs.o_underflow_reset.re,
If(selected & (self.cri.cmd == cri.commands["o_underflow_reset"]),
underflow.eq(0)),
If(selected & self.kcsrs.o_sequence_error_reset.re,
If(selected & (self.cri.cmd == cri.commands["o_sequence_error_reset"]),
sequence_error.eq(0)),
If(selected & self.kcsrs.o_collision_reset.re,
If(selected & (self.cri.cmd == cri.commands["o_collision_reset"]),
collision.eq(0)),
If(selected & self.kcsrs.o_busy_reset.re,
If(selected & (self.cri.cmd == cri.commands["o_busy_reset"]),
busy.eq(0)),
If(o_manager.underflow, underflow.eq(1)),
If(o_manager.sequence_error, sequence_error.eq(1)),
@@ -368,17 +372,17 @@ def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
else:
i_datas.append(0)
if channel.interface.i.timestamped:
ts_shift = (len(self.kcsrs.i_timestamp.status)
ts_shift = (len(self.cri.i_timestamp)
- len(i_manager.ev.timestamp))
i_timestamps.append(i_manager.ev.timestamp << ts_shift)
else:
i_timestamps.append(0)

self.comb += i_manager.re.eq(selected & self.kcsrs.i_re.re)
self.comb += i_manager.re.eq(selected & (self.cri.cmd == cri.commands["read"]))

overflow = Signal()
self.sync.rsys += [
If(selected & self.kcsrs.i_overflow_reset.re,
If(selected & (self.cri.cmd == cri.commands["i_overflow_reset"]),
overflow.eq(0)),
If(i_manager.overflow,
overflow.eq(1))
@@ -389,20 +393,11 @@ def __init__(self, channels, full_ts_width=63, guard_io_cycles=20):
i_datas.append(0)
i_timestamps.append(0)
i_statuses.append(0)
if data_width:
self.comb += self.kcsrs.i_data.status.eq(Array(i_datas)[sel])
self.comb += [
self.kcsrs.i_timestamp.status.eq(Array(i_timestamps)[sel]),
self.kcsrs.o_status.status.eq(Array(o_statuses)[sel]),
self.kcsrs.i_status.status.eq(Array(i_statuses)[sel])
self.cri.i_data.eq(Array(i_datas)[sel]),
self.cri.i_timestamp.eq(Array(i_timestamps)[sel]),
self.cri.o_status.eq(Array(o_statuses)[sel]),
self.cri.i_status.eq(Array(i_statuses)[sel])
]

# Counter access
self.sync += \
If(self.kcsrs.counter_update.re,
self.kcsrs.counter.status.eq(self.counter.value_sys
<< fine_ts_width)
)

def get_csrs(self):
return self.kcsrs.get_csrs()
self.cri.counter.eq(self.counter.value_sys << fine_ts_width)
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